Merge branch 'pci-driver' into 'master'

Merge interfacing CAN FD core to PCI Express bus

Closes #216

See merge request illeondr/CAN_FD_IP_Core!179

driver/ctu_can_fd_hw.c

@@ -55,12 +55,12 @@ void ctu_can_fd_write32_be(struct ctucanfd_priv *priv, enum ctu_can_fd_can_regis
 
 u32 ctu_can_fd_read32(struct ctucanfd_priv *priv, enum ctu_can_fd_can_registers reg)
 {
-	return ioread32((const char *)priv->mem_base + reg);
+	return ioread32((char *)priv->mem_base + reg);
 }
 
 u32 ctu_can_fd_read32_be(struct ctucanfd_priv *priv, enum ctu_can_fd_can_registers reg)
 {
-	return ioread32be((const char *)priv->mem_base + reg);
+	return ioread32be((char *)priv->mem_base + reg);
 }
 
 /*
@@ -208,6 +208,7 @@ void ctu_can_fd_enable(struct ctucanfd_priv *priv, bool enable)
 void ctu_can_fd_reset(struct ctucanfd_priv *priv)
 {
 	union ctu_can_fd_mode_command_status_settings mode;
+	mode.u32 = 0;
 	mode.s.rst = 1;
 	/* it does not matter that we overwrite the rest of the reg - we're resetting */
 	priv->write_reg(priv, CTU_CAN_FD_MODE, mode.u32);

driver/ctu_can_fd_hw.h

@@ -286,11 +286,28 @@ static inline union ctu_can_fd_mode_command_status_settings ctu_can_get_status(s
 {
 	// MODE and STATUS are within the same word
 	union ctu_can_fd_mode_command_status_settings res;
-	res.u32 = ctu_can_fd_read32(priv, CTU_CAN_FD_MODE);
+	res.u32 = priv->read_reg(priv, CTU_CAN_FD_MODE);
 	return res;
 }
 
 
+/*
+ * Test if core is enabled..
+ *
+ * Arguments:
+ *	priv	Private info
+
+ * Returns:
+ *	Return true if core is in enabled/active state..
+ */
+static inline bool ctu_can_fd_is_enabled(struct ctucanfd_priv *priv)
+{
+	union ctu_can_fd_mode_command_status_settings reg;
+	reg.u32 = priv->read_reg(priv, CTU_CAN_FD_MODE);
+	return reg.s.ena == ENABLED;
+}
+
+
 /*
  * Reads the interrupt status vector from CTU CAN FD Core.
  *
@@ -303,7 +320,7 @@ static inline union ctu_can_fd_mode_command_status_settings ctu_can_get_status(s
 static inline union ctu_can_fd_int_stat ctu_can_fd_int_sts(struct ctucanfd_priv *priv)
 {
 	union ctu_can_fd_int_stat res;
-	res.u32 = ctu_can_fd_read32(priv, CTU_CAN_FD_INT_STAT);
+	res.u32 = priv->read_reg(priv, CTU_CAN_FD_INT_STAT);
 	return res;
 }
 
@@ -317,7 +334,33 @@ static inline union ctu_can_fd_int_stat ctu_can_fd_int_sts(struct ctucanfd_priv
  */
 static inline void ctu_can_fd_int_clr(struct ctucanfd_priv *priv, union ctu_can_fd_int_stat mask)
 {
-	ctu_can_fd_write32(priv, CTU_CAN_FD_INT_STAT, mask.u32);
+	priv->write_reg(priv, CTU_CAN_FD_INT_STAT, mask.u32);
+}
+
+
+/*
+ * Sets enable interrupt bits.
+ *
+ * Arguments:
+ *	priv	Private info
+ *	mask	Mask of interrupts which should be disabled.
+ */
+static inline void ctu_can_fd_int_ena_set(struct ctucanfd_priv *priv, union ctu_can_fd_int_stat mask)
+{
+	priv->write_reg(priv, CTU_CAN_FD_INT_ENA_SET, mask.u32);
+}
+
+
+/*
+ * Clears enable interrupt bits.
+ *
+ * Arguments:
+ *	priv	Private info
+ *	mask	Mask of interrupts which should be disabled.
+ */
+static inline void ctu_can_fd_int_ena_clr(struct ctucanfd_priv *priv, union ctu_can_fd_int_stat mask)
+{
+	priv->write_reg(priv, CTU_CAN_FD_INT_ENA_CLR, mask.u32);
 }
 
 
@@ -429,7 +472,7 @@ void ctu_can_fd_read_err_ctrs(struct ctucanfd_priv *priv, struct can_berr_counte
 static inline u16 ctu_can_fd_read_nom_errs(struct ctucanfd_priv *priv)
 {
 	union ctu_can_fd_err_norm_err_fd reg;
-	reg.u32 = ctu_can_fd_read32(priv, CTU_CAN_FD_ERR_NORM);
+	reg.u32 = priv->read_reg(priv, CTU_CAN_FD_ERR_NORM);
 	return reg.s.err_norm_val;
 }
 
@@ -446,7 +489,7 @@ static inline void ctu_can_fd_erase_nom_errs(struct ctucanfd_priv *priv)
 	union ctu_can_fd_ctr_pres reg;
 	reg.u32 = 0;
 	reg.s.enorm = 1;
-	ctu_can_fd_write32(priv, CTU_CAN_FD_CTR_PRES, reg.u32);
+	priv->write_reg(priv, CTU_CAN_FD_CTR_PRES, reg.u32);
 }
 
 
@@ -462,7 +505,7 @@ static inline void ctu_can_fd_erase_nom_errs(struct ctucanfd_priv *priv)
 static inline u16 ctu_can_fd_read_fd_errs(struct ctucanfd_priv *priv)
 {
 	union ctu_can_fd_err_norm_err_fd reg;
-	reg.u32 = ctu_can_fd_read32(priv, CTU_CAN_FD_ERR_NORM);
+	reg.u32 = priv->read_reg(priv, CTU_CAN_FD_ERR_NORM);
 	return reg.s.err_fd_val;
 }
 
@@ -478,7 +521,7 @@ static inline void ctu_can_fd_erase_fd_errs(struct ctucanfd_priv *priv)
 	union ctu_can_fd_ctr_pres reg;
 	reg.u32 = 0;
 	reg.s.efd = 1;
-	ctu_can_fd_write32(priv, CTU_CAN_FD_CTR_PRES, reg.u32);
+	priv->write_reg(priv, CTU_CAN_FD_CTR_PRES, reg.u32);
 }
 
 
@@ -567,7 +610,7 @@ void ctu_can_fd_set_range_filter(struct ctucanfd_priv *priv, canid_t low_th,
 static inline u16 ctu_can_fd_get_rx_fifo_size(struct ctucanfd_priv *priv)
 {
 	union ctu_can_fd_rx_mem_info reg;
-	reg.u32 = ctu_can_fd_read32(priv, CTU_CAN_FD_RX_MEM_INFO);
+	reg.u32 = priv->read_reg(priv, CTU_CAN_FD_RX_MEM_INFO);
 	return reg.s.rx_buff_size;
 }
 
@@ -583,7 +626,7 @@ static inline u16 ctu_can_fd_get_rx_fifo_size(struct ctucanfd_priv *priv)
 static inline u16 ctu_can_fd_get_rx_fifo_mem_free(struct ctucanfd_priv *priv)
 {
 	union ctu_can_fd_rx_mem_info reg;
-	reg.u32 = ctu_can_fd_read32(priv, CTU_CAN_FD_RX_MEM_INFO);
+	reg.u32 = priv->read_reg(priv, CTU_CAN_FD_RX_MEM_INFO);
 	return reg.s.rx_mem_free;
 }
 
@@ -599,7 +642,7 @@ static inline u16 ctu_can_fd_get_rx_fifo_mem_free(struct ctucanfd_priv *priv)
 static inline bool ctu_can_fd_is_rx_fifo_empty(struct ctucanfd_priv *priv)
 {
 	union ctu_can_fd_rx_status_rx_settings reg;
-	reg.u32 = ctu_can_fd_read32(priv, CTU_CAN_FD_RX_STATUS);
+	reg.u32 = priv->read_reg(priv, CTU_CAN_FD_RX_STATUS);
 	return reg.s.rxe;
 }
 
@@ -615,7 +658,7 @@ static inline bool ctu_can_fd_is_rx_fifo_empty(struct ctucanfd_priv *priv)
 static inline bool ctu_can_fd_is_rx_fifo_full(struct ctucanfd_priv *priv)
 {
 	union ctu_can_fd_rx_status_rx_settings reg;
-	reg.u32 = ctu_can_fd_read32(priv, CTU_CAN_FD_RX_STATUS);
+	reg.u32 = priv->read_reg(priv, CTU_CAN_FD_RX_STATUS);
 	return reg.s.rxf;
 }
 
@@ -631,7 +674,7 @@ static inline bool ctu_can_fd_is_rx_fifo_full(struct ctucanfd_priv *priv)
 static inline u16 ctu_can_fd_get_rx_frame_count(struct ctucanfd_priv *priv)
 {
 	union ctu_can_fd_rx_status_rx_settings reg;
-	reg.u32 = ctu_can_fd_read32(priv, CTU_CAN_FD_RX_STATUS);
+	reg.u32 = priv->read_reg(priv, CTU_CAN_FD_RX_STATUS);
 	return reg.s.rxfrc;
 }
 
@@ -646,6 +689,37 @@ static inline u16 ctu_can_fd_get_rx_frame_count(struct ctucanfd_priv *priv)
 void ctu_can_fd_set_rx_tsop(struct ctucanfd_priv *priv, enum ctu_can_fd_rx_settings_rtsop val);
 
 
+/*
+ * Reads the first word of CAN Frame from RX FIFO Buffer.
+ *
+ * Arguments:
+ *	priv	Private info
+ *
+ * Returns:
+ *	The firts word of received frame
+ */
+static inline union ctu_can_fd_frame_form_w ctu_can_fd_read_rx_ffw(struct ctucanfd_priv *priv)
+{
+	union ctu_can_fd_frame_form_w ffw;
+	ffw.u32 = priv->read_reg(priv, CTU_CAN_FD_RX_DATA);
+	return ffw;
+}
+
+/*
+ * Reads one word of CAN Frame from RX FIFO Buffer.
+ *
+ * Arguments:
+ *	priv	Private info
+ *
+ * Returns:
+ *	One wword of received frame
+ */
+static inline u32 ctu_can_fd_read_rx_word(struct ctucanfd_priv *priv)
+{
+	return priv->read_reg(priv, CTU_CAN_FD_RX_DATA);
+}
+
+
 /*
  * Reads CAN Frame from RX FIFO Buffer and stores it to a buffer.
  *
@@ -781,7 +855,7 @@ bool ctu_can_fd_insert_frame(struct ctucanfd_priv *priv, const struct canfd_fram
 static inline u16 ctu_can_fd_get_tran_delay(struct ctucanfd_priv *priv)
 {
 	union ctu_can_fd_trv_delay_ssp_cfg reg;
-	reg.u32 = ctu_can_fd_read32(priv, CTU_CAN_FD_TRV_DELAY);
+	reg.u32 = priv->read_reg(priv, CTU_CAN_FD_TRV_DELAY);
 	return reg.s.trv_delay_value;
 }
 
@@ -797,7 +871,7 @@ static inline u16 ctu_can_fd_get_tran_delay(struct ctucanfd_priv *priv)
 static inline u32 ctu_can_fd_get_tx_frame_ctr(struct ctucanfd_priv *priv)
 {
 	union ctu_can_fd_tx_counter reg;
-	reg.u32 = ctu_can_fd_read32(priv, CTU_CAN_FD_TX_COUNTER);
+	reg.u32 = priv->read_reg(priv, CTU_CAN_FD_TX_COUNTER);
 	return reg.s.tx_counter_val;
 }
 
@@ -813,7 +887,7 @@ static inline u32 ctu_can_fd_get_tx_frame_ctr(struct ctucanfd_priv *priv)
 static inline u32 ctu_can_fd_get_rx_frame_ctr(struct ctucanfd_priv *priv)
 {
 	union ctu_can_fd_rx_counter reg;
-	reg.u32 = ctu_can_fd_read32(priv, CTU_CAN_FD_RX_COUNTER);
+	reg.u32 = priv->read_reg(priv, CTU_CAN_FD_RX_COUNTER);
 	return reg.s.rx_counter_val;
 }
 
@@ -829,7 +903,7 @@ static inline u32 ctu_can_fd_get_rx_frame_ctr(struct ctucanfd_priv *priv)
 static inline union ctu_can_fd_debug_register ctu_can_fd_read_debug_info(struct ctucanfd_priv *priv)
 {
 	union ctu_can_fd_debug_register reg;
-	reg.u32 = ctu_can_fd_read32(priv, CTU_CAN_FD_DEBUG_REGISTER);
+	reg.u32 = priv->read_reg(priv, CTU_CAN_FD_DEBUG_REGISTER);
 	return reg;
 }
 

driver/ctu_can_fd_linux_defs.h

@@ -41,13 +41,15 @@
 #include <stdint.h>
 #include <stdio.h>
 #include <stddef.h>
-//#include <linux/types.h>
+#include <linux/types.h>
 #include <linux/socket.h>
 #include <arpa/inet.h>
 #define likely(x) __builtin_expect(!!(x), 1)
 #define unlikely(x) __builtin_expect(!!(x), 0)
 #define __iomem volatile
 
+#ifndef _ASM_GENERIC_INT_LL64_H
+
 typedef uint8_t   __u8;
 typedef uint16_t  __u16;
 typedef uint32_t  __u32;
@@ -58,6 +60,8 @@ typedef int16_t  __s16;
 typedef int32_t  __s32;
 typedef int64_t  __s64;
 
+#endif
+
 typedef __u8  u8;
 typedef __u16 u16;
 typedef __u32 u32;

driver/linux/Makefile

+CROSS_COMPILE= arm-linux-gnueabihf-
 KDIR ?= /home/mjerabek/projects/kernel/linux-4.15-build/zynq
+ARCH=arm
+
+#KDIR ?= /lib/modules/$(shell uname -r)/build
+#ARCH ?= x86_64
+
 default:
-	$(MAKE) -C $(KDIR) ARCH=arm CROSS_COMPILE=arm-linux-gnueabihf- M=$$PWD
+	$(MAKE) -C $(KDIR) ARCH=$(ARCH) CROSS_COMPILE=$(CROSS_COMPILE) M=$$PWD
 ifeq ($(shell hostname),hathi)
 	-rm -f /srv/nfs4/debian-armhf-devel/ctucanfd.ko
 	cp ctucanfd.ko /srv/nfs4/debian-armhf-devel/