Commit 298aac6e authored by Martin Jeřábek's avatar Martin Jeřábek

axi: fix rdata & rresp signals

parent 5d7ff8ee
......@@ -98,7 +98,6 @@ architecture rtl of axi_ifc is
signal axi_bvalid : std_logic;
signal axi_araddr : std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
signal axi_arready : std_logic;
signal axi_rdata : std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal axi_rresp : std_logic_vector(1 downto 0);
signal axi_rvalid : std_logic;
......@@ -115,7 +114,6 @@ begin
S_AXI_BRESP <= axi_bresp;
S_AXI_BVALID <= axi_bvalid;
S_AXI_ARREADY <= axi_arready;
S_AXI_RDATA <= axi_rdata;
S_AXI_RRESP <= axi_rresp;
S_AXI_RVALID <= axi_rvalid;
......@@ -169,6 +167,7 @@ begin
axi_arready <= '1';
axi_rvalid <= '1';
axi_rresp <= "00"; -- OK
elsif (want_to_write = '1') then
reg_addr_o <= S_AXI_AWADDR;
reg_be_o <= S_AXI_WSTRB;
......
......@@ -16,7 +16,7 @@ entity CTU_CAN_FD_v1_0 is
);
port(
-- system clock and reset from AXI
int : out std_logic;
irq : out std_logic;
CAN_tx : out std_logic;
CAN_rx : in std_logic;
time_quanta_clk : out std_logic;
......@@ -155,7 +155,7 @@ begin
swr => reg_wren,
sbe => reg_be,
int => int,
int => irq,
CAN_tx => CAN_tx,
CAN_rx => CAN_rx,
......
......@@ -245,6 +245,28 @@
</spirit:portMap>
</spirit:portMaps>
</spirit:busInterface>
<spirit:busInterface>
<spirit:name>irq</spirit:name>
<spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="interrupt" spirit:version="1.0"/>
<spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="interrupt_rtl" spirit:version="1.0"/>
<spirit:master/>
<spirit:portMaps>
<spirit:portMap>
<spirit:logicalPort>
<spirit:name>INTERRUPT</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
<spirit:name>irq</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
</spirit:portMaps>
<spirit:parameters>
<spirit:parameter>
<spirit:name>SENSITIVITY</spirit:name>
<spirit:value spirit:id="BUSIFPARAM_VALUE.IRQ.SENSITIVITY" spirit:choiceRef="choice_list_99a1d2b9">LEVEL_HIGH</spirit:value>
</spirit:parameter>
</spirit:parameters>
</spirit:busInterface>
</spirit:busInterfaces>
<spirit:memoryMaps>
<spirit:memoryMap>
......@@ -267,26 +289,6 @@
</spirit:parameters>
</spirit:addressBlock>
</spirit:memoryMap>
<spirit:memoryMap>
<spirit:name>S_AXI_INTR</spirit:name>
<spirit:addressBlock>
<spirit:name>S_AXI_INTR_reg</spirit:name>
<spirit:baseAddress spirit:format="long" spirit:resolve="user">0</spirit:baseAddress>
<spirit:range spirit:format="long">4096</spirit:range>
<spirit:width spirit:format="long">32</spirit:width>
<spirit:usage>register</spirit:usage>
<spirit:parameters>
<spirit:parameter>
<spirit:name>OFFSET_BASE_PARAM</spirit:name>
<spirit:value spirit:id="ADDRBLOCKPARAM_VALUE.S_AXI_INTR.S_AXI_INTR_REG.OFFSET_BASE_PARAM">C_S_AXI_INTR_BASEADDR</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>OFFSET_HIGH_PARAM</spirit:name>
<spirit:value spirit:id="ADDRBLOCKPARAM_VALUE.S_AXI_INTR.S_AXI_INTR_REG.OFFSET_HIGH_PARAM">C_S_AXI_INTR_HIGHADDR</spirit:value>
</spirit:parameter>
</spirit:parameters>
</spirit:addressBlock>
</spirit:memoryMap>
</spirit:memoryMaps>
<spirit:model>
<spirit:views>
......@@ -346,7 +348,7 @@
</spirit:views>
<spirit:ports>
<spirit:port>
<spirit:name>int</spirit:name>
<spirit:name>irq</spirit:name>
<spirit:wire>
<spirit:direction>out</spirit:direction>
<spirit:wireTypeDefs>
......@@ -782,6 +784,13 @@
<spirit:name>choice_list_6fc15197</spirit:name>
<spirit:enumeration>32</spirit:enumeration>
</spirit:choice>
<spirit:choice>
<spirit:name>choice_list_99a1d2b9</spirit:name>
<spirit:enumeration>LEVEL_HIGH</spirit:enumeration>
<spirit:enumeration>LEVEL_LOW</spirit:enumeration>
<spirit:enumeration>EDGE_RISING</spirit:enumeration>
<spirit:enumeration>EDGE_FALLING</spirit:enumeration>
</spirit:choice>
<spirit:choice>
<spirit:name>choice_pairs_ce1226b1</spirit:name>
<spirit:enumeration spirit:text="true">1</spirit:enumeration>
......@@ -1142,18 +1151,18 @@
<xilinx:taxonomy>AXI_Peripheral</xilinx:taxonomy>
</xilinx:taxonomies>
<xilinx:displayName>CTU_CAN_FD_v1.0</xilinx:displayName>
<xilinx:coreRevision>4</xilinx:coreRevision>
<xilinx:coreCreationDateTime>2018-02-12T18:34:21Z</xilinx:coreCreationDateTime>
<xilinx:coreRevision>7</xilinx:coreRevision>
<xilinx:coreCreationDateTime>2018-03-01T11:00:14Z</xilinx:coreCreationDateTime>
<xilinx:tags>
<xilinx:tag xilinx:name="user.org:user:CTU_CAN_FD:1.0_ARCHIVE_LOCATION">/home/martin/projects/cvut/can-fd/CAN_FD_IP_Core/src/ip/ip/CTU_CAN_FD_1.0</xilinx:tag>
<xilinx:tag xilinx:name="user.org:user:CTU_CAN_FD:1.0_ARCHIVE_LOCATION">/home/martin/projects/cvut/bakalarka/canbench-sw/modules/CTU_CAN_FD/src/ip/CTU_CAN_FD_1.0</xilinx:tag>
</xilinx:tags>
</xilinx:coreExtensions>
<xilinx:packagingInfo>
<xilinx:xilinxVersion>2017.4</xilinx:xilinxVersion>
<xilinx:checksum xilinx:scope="busInterfaces" xilinx:value="2bfdb5d5"/>
<xilinx:checksum xilinx:scope="memoryMaps" xilinx:value="74e1175e"/>
<xilinx:checksum xilinx:scope="busInterfaces" xilinx:value="544191d5"/>
<xilinx:checksum xilinx:scope="memoryMaps" xilinx:value="ed1368d5"/>
<xilinx:checksum xilinx:scope="fileGroups" xilinx:value="72317b20"/>
<xilinx:checksum xilinx:scope="ports" xilinx:value="b40ef9b0"/>
<xilinx:checksum xilinx:scope="ports" xilinx:value="dd2ca01e"/>
<xilinx:checksum xilinx:scope="hdlParameters" xilinx:value="354d864e"/>
<xilinx:checksum xilinx:scope="parameters" xilinx:value="bef1e4ab"/>
</xilinx:packagingInfo>
......
Markdown is supported
0% or .
You are about to add 0 people to the discussion. Proceed with caution.
Finish editing this message first!
Please register or to comment