Commit 23b5ae4a authored by Ille, Ondrej, Ing.'s avatar Ille, Ondrej, Ing.

Merge branch 'Data_brief_v_2.1' into 'master'

Data brief v 2.1

See merge request illeondr/CAN_FD_IP_Core!171
parents 7db6025a e7a1a4c3
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#LyX 2.3 created this file. For more info see http://www.lyx.org/
\lyxformat 544
\begin_document
\begin_header
\save_transient_properties true
\origin unavailable
\textclass book
\begin_preamble
\usepackage{fancyhdr}
\pagestyle{fancy}
\usepackage{colortbl}
\definecolor{gray}{RGB}{230,230, 230}
\usepackage{subcaption}
\usepackage{cprotect}
\end_preamble
\use_default_options true
\begin_modules
customHeadersFooters
\end_modules
\maintain_unincluded_children false
\language english
\language_package default
\inputencoding auto
\fontencoding global
\font_roman "default" "default"
\font_sans "default" "default"
\font_typewriter "lmtt" "default"
\font_math "auto" "auto"
\font_default_family sfdefault
\use_non_tex_fonts false
\font_sc false
\font_osf false
\font_sf_scale 100 100
\font_tt_scale 100 100
\use_microtype false
\use_dash_ligatures false
\graphics default
\default_output_format default
\output_sync 0
\bibtex_command default
\index_command default
\paperfontsize default
\spacing other 1.1
\use_hyperref true
\pdf_author "Ille Ondrej"
\pdf_subject "CAN FD IP function"
\pdf_keywords "CAN, Flexible data rate,"
\pdf_bookmarks true
\pdf_bookmarksnumbered true
\pdf_bookmarksopen false
\pdf_bookmarksopenlevel 1
\pdf_breaklinks false
\pdf_pdfborder true
\pdf_colorlinks false
\pdf_backref false
\pdf_pdfusetitle true
\papersize default
\use_geometry true
\use_package amsmath 1
\use_package amssymb 1
\use_package cancel 1
\use_package esint 1
\use_package mathdots 1
\use_package mathtools 1
\use_package mhchem 1
\use_package stackrel 1
\use_package stmaryrd 1
\use_package undertilde 1
\cite_engine basic
\cite_engine_type default
\biblio_style plain
\use_bibtopic false
\use_indices false
\paperorientation portrait
\suppress_date false
\justification true
\use_refstyle 1
\use_minted 0
\index Index
\shortcut idx
\color #008000
\end_index
\leftmargin 2cm
\topmargin 3cm
\rightmargin 2cm
\bottommargin 3cm
\headheight 2cm
\secnumdepth 2
\tocdepth 5
\paragraph_separation skip
\defskip smallskip
\is_math_indent 0
\math_numbering_side default
\quotes_style english
\dynamic_quotes 0
\papercolumns 1
\papersides 1
\paperpagestyle headings
\tracking_changes false
\output_changes false
\html_math_output 0
\html_css_as_file 0
\html_be_strict false
\end_header
\begin_body
\begin_layout Chapter*
\noindent
CAN FLEXIBLE DATA-RATE IP CORE
\begin_inset Newline newline
\end_inset
\size large
PRODUCT BRIEF v2.1
\end_layout
\begin_layout Standard
\noindent
\begin_inset ERT
status open
\begin_layout Plain Layout
\backslash
thispagestyle{fancy}
\end_layout
\end_inset
\end_layout
\begin_layout Left Header
\noindent
\end_layout
\begin_layout Right Header
\noindent
Martin Jerabek, Ondrej Ille
\end_layout
\begin_layout Section*
\noindent
Overview
\end_layout
\begin_layout Standard
\paragraph_spacing single
CAN Flexible Data-Rate IP Core connects functionality of CAN 2.0, CAN FD
1.0 and ISO CAN FD specification in a light - weight IP Core.
It is a soft-core IP Core written in VHDL, with no vendor specific libraries
needed.
The main target of usage are FPGA applications, and the core RTL is freely
available under MIT License in
\color blue
\begin_inset CommandInset href
LatexCommand href
name "Gitlab repository of CTU FEE"
target "https://gitlab.fel.cvut.cz/illeondr/CAN_FD_IP_Core"
literal "false"
\end_inset
\color inherit
.
It is optimized for inference of native hardware blocks such as SRAM memories
and DSP blocks.
Generic settings achieve high level of flexibility before synthesis.
\end_layout
\begin_layout Standard
\paragraph_spacing single
The IP Core is accessed as a slave memory mapped peripheria via Avalon bus
or APB.
Easy manipulation with the core is achieved by using hardware buffers for
CAN frames.
One FIFO RX buffer is available, and 4 TX buffers are available.
Timestamps can be captured for various events on the CAN bus and transmission
of CAN frames can be triggered by external timestamp.
Three Bit filters and one Range filter is available for HW filtration of
received CAN frames.
The Core was synthesized in low-end Xilinx and Altera FPGAs with maximal
operating frequencies above 100 MHz.
\end_layout
\begin_layout Standard
\paragraph_spacing single
CTU CAN FD also contains a Linux SocketCAN driver.
The design contains its own testing framework which is based on Vunit test
framework and simulated via GHDL or Modelsim.
At the moment the development team of CTU CAN FD is working on ISO conformance
testing to guarantee proper operation in commercial applications.
\end_layout
\begin_layout Standard
\begin_inset VSpace bigskip
\end_inset
\end_layout
\begin_layout Standard
\noindent
\begin_inset Float figure
placement h
wide false
sideways false
status open
\begin_layout Plain Layout
\noindent
\align center
\begin_inset Graphics
filename ../pics/Visio_generated/IP_core_block_diagram.pdf
lyxscale 10
scale 55
\end_inset
\end_layout
\end_inset
\end_layout
\begin_layout Section*
\noindent
Features
\end_layout
\begin_layout Itemize
\paragraph_spacing other 0.5
\noindent
CAN 2.0, CAN FD 1.0 and ISO CAN FD
\end_layout
\begin_layout Itemize
\paragraph_spacing other 0.5
\noindent
RTL VHDL
\end_layout
\begin_layout Itemize
\paragraph_spacing other 0.5
\noindent
Pre-synthesis configurable features
\end_layout
\begin_layout Itemize
\paragraph_spacing other 0.5
\noindent
Avalon compatible memory bus, APB
\end_layout
\begin_layout Itemize
\paragraph_spacing other 0.5
\noindent
Timestamping and transmission at given time
\end_layout
\begin_layout Itemize
\paragraph_spacing other 0.5
\noindent
Optional event and error logging
\end_layout
\begin_layout Itemize
\paragraph_spacing other 0.5
\noindent
Fault confinement state manipulation
\end_layout
\begin_layout Itemize
\paragraph_spacing other 0.5
\noindent
Transceiver delay measurement
\end_layout
\begin_layout Itemize
\paragraph_spacing other 0.5
\noindent
Size of 1700-2300 ALMs (Intel) , 2500 - 3300 LUTs (Xilinx)
\end_layout
\begin_layout Itemize
\paragraph_spacing other 0.5
\noindent
3 500 - 138 000 SRAM memory bits (Intel), 2.5 - 6 BRAMS (Xilinx)
\end_layout
\begin_layout Itemize
\paragraph_spacing other 0.5
\noindent
Synchronization output with time quantum
\end_layout
\begin_layout Itemize
\paragraph_spacing other 0.5
\noindent
Filtering of received frames
\end_layout
\begin_layout Itemize
\paragraph_spacing other 0.5
\noindent
Listen-only mode, Self-test mode, Acknowledge forbidden mode
\end_layout
\begin_layout Itemize
\paragraph_spacing other 0.5
\noindent
Up to 14 Mbit in
\begin_inset Quotes eld
\end_inset
Data
\begin_inset Quotes erd
\end_inset
Bit-Rate (with 100 MHz Core clock)
\end_layout
\begin_layout Itemize
\paragraph_spacing other 0.5
\noindent
Linux SocketCAN driver available
\end_layout
\end_body
\end_document
......@@ -38,32 +38,23 @@
## Script for evaluation of CTU CAN FD IP Core size in Xilinx and Intel
## FPGAs. Supports Quartus Prime (Intel) and Vivado (Xilinx).
##
## Common manual:
## 1. Set global variable TOOL_NAME (see in script) to "Quartus" or
## "Vivado" based on which tool you want to use!
## 2. Follow manual for dedicated tool below
##
## Manual for Quartus:
## 1. Open "synthesis/Quartus/Benchmark_project.qpf"
## 2. Turn on TCL Command line: View->Utility Windows->TCL Console
## 3. Open available TCL scripts: Tools->TCL Scripts
## 4. Run available "Resource_Benchmark.tcl" script
## 5. Observe outputs in TCL console.
## 1. Set Environment variable $TOOL_NAME = "Quartus"
## 2. Open "synthesis/Quartus/Benchmark_project.qpf"
## 3. Turn on TCL Command line: View->Utility Windows->TCL Console
## 4. Open available TCL scripts: Tools->TCL Scripts
## 5. Run available "Resource_Benchmark.tcl" script
## 6. Observe outputs in TCL console.
##
## Manual for Vivado:
## 1.
## 1. Set Environment variable $TOOL_NAME = "Vivado"
## 2. Wait till the end and check results in runs.
##
## Quartus TCL script for automation of core resource requirements.
## Execute the script in Quartus project: Benchmark_project located
## in synthesis/Quartus.
################################################################################
## Tool in which script will be used.
## Options: "Quartus", "Vivado"
set TOOL_NAME "Vivado"
proc intel_benchmark {} {
......@@ -93,12 +84,12 @@ proc intel_benchmark {} {
# Load timing Analysis of 85 ° Slow
set panel_name {TimeQuest Timing Analyzer||Slow 1100mV 85C Model||Slow 1100mV 85C Model Fmax Summary}
set panel_id [get_report_panel_id $panel_name]
set panel_id [get_report_panel_id $panel_name]
set max_freq [get_report_panel_data -row 1 -col 0 -id $panel_id]
# Load FPGA resource usage
set aluts [get_fitter_resource_usage -alut -used]
set aregs [get_fitter_resource_usage -reg -used]
set aregs [get_fitter_resource_usage -reg -used]
set alms [get_fitter_resource_usage -alm -used]
set mbits [get_fitter_resource_usage -mem_bit -used]
......@@ -110,6 +101,10 @@ proc intel_benchmark {} {
[list "Mbits" $mbits]
]
foreach cfg_res $results {
puts $cfg_res
}
# VERY IMPORTANT! Report must be unloaded! Otherwise next Load
# of report (after next synthesis) will crash Quartus (16.1)!!
unload_report
......@@ -119,6 +114,10 @@ proc intel_benchmark {} {
proc xilinx_benchmark {} {
global CFG_LIST
global PARAM_NAMES
global results
puts "Running Vivado Benchmark!"
#List through CTU CAN FD configurations
......@@ -126,21 +125,26 @@ proc xilinx_benchmark {} {
set act_cfg [lindex $config 0]
puts "Configuration name: ${act_cfg}"
set run_name "benchmark"
set run_name "Benchmark:${act_cfg}"
#Create new run
create_run -flow {Vivado Synthesis 2013} $run_name
reset_run $run_name
# Delete old run if existing, create new run!
delete_runs -quiet $run_name
create_run -flow {Vivado Synthesis 2013} $run_name
current_run [get_runs $run_name]
# Set configuration to top level entity
set parm_dict {}
foreach par_name $PARAM_NAMES par_val $config {
set_property generic {$par_name=$par_val} [current_fileset]
}
puts "${par_name} : ${par_val}"
dict append parm_dict $par_name=$par_val
}
set_property generic $parm_dict [current_fileset]
# Launch run
reset_run $run_name
launch_run $run_name
wait_on_run $run_name
}
}
......@@ -179,23 +183,23 @@ set PARAM_NAMES [ list "dummy" \
]
## List of synthesis configurations
set CFG_LIST [ list [ list "Minimal configuration" \
set CFG_LIST [ list [ list "Minimal_configuration" \
false 32 true 1\
false false false false 8
] \
[ list "Medium configuration" \
[ list "Medium_configuration" \
false 256 true 1\
false false true true 8
] \
[ list "Full configuration" \
[ list "Full_configuration" \
false 4096 true 1\
true true true true 8
] \
[ list "Full configuration + Small logger" \
[ list "Full_configuration_Small_logger" \
true 4096 true 1\
true true true true 8
] \
[ list "Full configuration + Big logger" \
[ list "Full_configuration_Big_logger" \
true 4096 true 1\
true true true true 64
]
......@@ -209,11 +213,6 @@ set CFG_LIST [ list [ list "Minimal configuration" \
puts "Starting CTU CAN FD FPGA Benchmark. Selected tool:"
puts $TOOL_NAME
#if ($TOOL_NAME /= "Vivado" and $TOOL_NAME /= "Quartus"){
# puts "Invalid Tool selected -> Exiting!"
# exit
#}
if {$TOOL_NAME == "Quartus"} {
intel_benchmark
}
......
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