Commit 220e45d3 authored by Ille, Ondrej, Ing.'s avatar Ille, Ondrej, Ing.

Merge branch '357-non-synchronisation-on-dominant-transmitted-bit' into 'master'

src,test: Fix No positive resynchronisation.

Closes #357

See merge request !339
parents e4421ac8 e5886ab8
Pipeline #20205 passed with stage
in 16 seconds
......@@ -2657,7 +2657,7 @@ ISO11898-1 2015 defines three implementation types of CAN protocol: Classical
CAN, CAN FD tolerant and CAN FD enabled.
CTU CAN FD supports all three implementation types and compliance to each
implementation can be changed via MODE[FDE] and SETTINGS[PEX] registers.
Both of these registers chall be modified only when SETTINGS[ENA] = 0.
Both of these registers shall be modified only when SETTINGS[ENA] = 0.
\end_layout
\begin_layout Standard
......@@ -2726,7 +2726,7 @@ cellcolor{gray}
\begin_inset Text
\begin_layout Plain Layout
SETTING[PEX]
SETTING [PEX]
\begin_inset ERT
status open
......@@ -2985,6 +2985,13 @@ Note When CTU CAN FD is configured as Classical CAN / CAN FD tolerant node,
SETTINGS[NISOFD] register has no effect.
\end_layout
\begin_layout Description
Note According to 10.9.10 of ISO11898-1 2015, CAN FD Enabled implementation
shall not be set to a mode where it behaves as CAN FD tolerant implementation.
It is therefore users responsibility to use this option only for evaluation
/ debugging purposes!
\end_layout
\begin_layout Subsection
Minimum bit time
\end_layout
......
......@@ -577,7 +577,6 @@ begin
nbt_ctrs_en => nbt_ctrs_en, -- OUT
dbt_ctrs_en => dbt_ctrs_en, -- OUT
sync_control => sync_control_i, -- OUT
no_pos_resync => no_pos_resync, -- OUT
ssp_reset => ssp_reset_i, -- OUT
tran_delay_meas => tran_delay_meas_i, -- OUT
tran_valid => tran_valid_i, -- OUT
......@@ -887,6 +886,12 @@ begin
RECESSIVE when (drv_bus_mon_ena = '1') else
bst_data_out;
----------------------------------------------------------------------------
-- Node transmitting dominant bit does shall not re-synchronize as a result
-- of dominant transmitted bit.
----------------------------------------------------------------------------
no_pos_resync <= '1' when (tx_data_wbs_i = DOMINANT) else
'0';
----------------------------------------------------------------------------
-- STATUS Bus Implementation
......
......@@ -379,9 +379,6 @@ entity protocol_control is
-- Resynchronisation
sync_control :out std_logic_vector(1 downto 0);
-- No Resynchronisation due to positive phase error
no_pos_resync :out std_logic;
-- Clear the Shift register for secondary sampling point.
ssp_reset :out std_logic;
......@@ -800,7 +797,6 @@ begin
nbt_ctrs_en => nbt_ctrs_en, -- OUT
dbt_ctrs_en => dbt_ctrs_en, -- OUT
sync_control => sync_control, -- OUT
no_pos_resync => no_pos_resync, -- OUT
ssp_reset => ssp_reset, -- OUT
tran_delay_meas => tran_delay_meas, -- OUT
tran_valid => tran_valid, -- OUT
......
......@@ -488,9 +488,6 @@ entity protocol_control_fsm is
-- Resynchronisation)
sync_control :out std_logic_vector(1 downto 0);
-- No Resynchronisation due to positive phase error
no_pos_resync :out std_logic;
-- Clear the Shift register for secondary sampling point.
ssp_reset :out std_logic;
......@@ -2907,11 +2904,6 @@ begin
else
'0';
-- No positive resynchronisation for transmitter of dominant bit!
no_pos_resync <= '1' when (is_transmitter = '1' and tx_data_wbs = DOMINANT)
else
'0';
rx_clear <= '1' when (rx_clear_i = '1' and rx_trigger = '1')
else
'0';
......
......@@ -1870,9 +1870,6 @@ package can_components is
-- Resynchronisation)
sync_control :out std_logic_vector(1 downto 0);
-- No Resynchronisation due to positive phase error
no_pos_resync :out std_logic;
-- Clear the Shift register for secondary sampling point.
ssp_reset :out std_logic;
......@@ -2224,9 +2221,6 @@ package can_components is
-- Resynchronisation
sync_control :out std_logic_vector(1 downto 0);
-- No Resynchronisation due to positive phase error
no_pos_resync :out std_logic;
-- Clear the Shift register for secondary sampling point.
ssp_reset :out std_logic;
......
......@@ -114,6 +114,9 @@ package body command_frcrst_feature is
CAN_wait_frame_sent(ID_1, mem_bus(1));
CAN_wait_bus_idle(ID_1, mem_bus(1));
CAN_wait_bus_idle(ID_2, mem_bus(2));
read_traffic_counters(traff_ctrs_2, ID_2, mem_bus(2));
check(traff_ctrs_2.tx_frames /= 0, "TX frame counter not 0!");
......
......@@ -173,6 +173,12 @@ package body error_rules_e_feature is
CAN_generate_frame(rand_ctr, CAN_frame);
CAN_send_frame(CAN_frame, 1, ID_1, mem_bus(1), frame_sent);
CAN_wait_pc_state(pc_deb_intermission, ID_2, mem_bus(2));
-----------------------------------------------------------------------
-- Fix: We must wait for one more bit since Node 1 might understood
-- this as Error condition.
-----------------------------------------------------------------------
CAN_wait_sample_point(iout(2).stat_bus, false);
-- Force Dominant -> Overload condition!
force_bus_level(DOMINANT, so.bl_force, so.bl_inject);
......
......@@ -166,6 +166,10 @@ package body rx_status_feature is
CAN_send_frame(CAN_frame, 1, ID_2, mem_bus(2), frame_sent);
CAN_wait_frame_sent(ID_1, mem_bus(1));
CAN_wait_bus_idle(ID_1, mem_bus(1));
CAN_wait_bus_idle(ID_2, mem_bus(2));
number_frms_sent := number_frms_sent + 1;
in_RX_buf := in_RX_buf + CAN_frame.rwcnt + 1;
......
......@@ -124,7 +124,10 @@ package body status_rxne_feature is
for i in 0 to num_frames - 1 loop
send_TXT_buf_cmd(buf_set_ready, 1, ID_2, mem_bus(2));
CAN_wait_frame_sent(ID_1, mem_bus(1));
CAN_wait_frame_sent(ID_2, mem_bus(2));
CAN_wait_bus_idle(ID_1, mem_bus(1));
CAN_wait_bus_idle(ID_2, mem_bus(2));
get_controller_status(stat_1, ID_1, mem_bus(1));
check(stat_1.receive_buffer, "RX Buffer not empty");
......
......@@ -164,7 +164,10 @@ package body trv_delay_feature is
CAN_TX_frame.brs := BR_SHIFT;
CAN_send_frame(CAN_TX_frame, 1, ID_1, mem_bus(1), frame_sent);
CAN_wait_frame_sent(ID_2, mem_bus(2));
CAN_wait_frame_sent(ID_1, mem_bus(1));
CAN_wait_bus_idle(ID_1, mem_bus(1));
CAN_wait_bus_idle(ID_2, mem_bus(2));
read_trv_delay(measured_delay, ID_1, mem_bus(1));
......@@ -187,7 +190,10 @@ package body trv_delay_feature is
ftr_tb_set_tran_delay(1255 ns, ID_1, so.ftr_tb_trv_delay);
CAN_send_frame(CAN_TX_frame, 1, ID_1, mem_bus(1), frame_sent);
CAN_wait_frame_sent(ID_2, mem_bus(2));
CAN_wait_frame_sent(ID_1, mem_bus(1));
CAN_wait_bus_idle(ID_1, mem_bus(1));
CAN_wait_bus_idle(ID_2, mem_bus(2));
read_trv_delay(measured_delay, ID_1, mem_bus(1));
......
......@@ -138,6 +138,11 @@ package body tx_from_intermission_feature is
CAN_wait_sample_point(iout(1).stat_bus, false);
CAN_wait_sample_point(iout(1).stat_bus, false);
-- This is needed to be sure that Node 2 also reached second sample
-- point of intermission. Otherwise, it would interpret this as
-- overload condition, and it would not turn reciever!
wait for 100 ns;
force_bus_level(DOMINANT, so.bl_force, so.bl_inject);
CAN_wait_sample_point(iout(1).stat_bus, false);
wait for 15 ns; -- To be sure sample point was processed!
......
......@@ -252,7 +252,6 @@ architecture Protocol_Control_unit_test of CAN_test is
-- Control signals
signal sp_control_1 : std_logic_vector(1 downto 0);
signal sync_control_1 : std_logic_vector(1 downto 0);
signal no_pos_resync_1 : std_logic;
signal ssp_reset_1 : std_logic;
signal tran_delay_meas_1 : std_logic;
signal tran_valid_1 : std_logic;
......@@ -360,7 +359,6 @@ architecture Protocol_Control_unit_test of CAN_test is
-- Control signals
signal sp_control_2 : std_logic_vector(1 downto 0);
signal sync_control_2 : std_logic_vector(1 downto 0);
signal no_pos_resync_2 : std_logic;
signal ssp_reset_2 : std_logic;
signal tran_delay_meas_2 : std_logic;
signal tran_valid_2 : std_logic;
......@@ -760,7 +758,6 @@ begin
-- Control signals
sp_control => sp_control_1,
sync_control => sync_control_1,
no_pos_resync => no_pos_resync_1,
ssp_reset => ssp_reset_1,
tran_delay_meas => tran_delay_meas_1,
tran_valid => tran_valid_1,
......@@ -880,7 +877,6 @@ begin
-- Control signals
sp_control => sp_control_2,
sync_control => sync_control_2,
no_pos_resync => no_pos_resync_2,
ssp_reset => ssp_reset_2,
tran_delay_meas => tran_delay_meas_2,
tran_valid => tran_valid_2,
......
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