Commit 1e206b2b authored by Ille, Ondrej, Ing.'s avatar Ille, Ondrej, Ing.

Separated traffic counters to stand-alone wrapper.

Used single adder for both counters and mux on input.
Added assert on mutual exclusion of simultaneous addition.
This should be always valid since "tran_valid" and "rec_valid"
occur in different part of CAN frame.
parent c3c508d2
......@@ -676,6 +676,22 @@ package CANcomponents is
end component;
----------------------------------------------------------------------------
-- Bus traffic counters
----------------------------------------------------------------------------
component bus_traffic_counters is
port(
signal clk_sys :in std_logic;
signal res_n :in std_logic;
signal clear_rx_ctr :in std_logic;
signal clear_tx_ctr :in std_logic;
signal inc_tx_ctr :in std_logic;
signal inc_rx_ctr :in std_logic;
signal tx_ctr :out std_logic_vector(31 downto 0);
signal rx_ctr :out std_logic_vector(31 downto 0)
);
end component;
----------------------------------------------------------------------------
-- Prescaler module
----------------------------------------------------------------------------
......
--------------------------------------------------------------------------------
--
-- CTU CAN FD IP Core
-- Copyright (C) 2015-2018
--
-- Authors:
-- Ondrej Ille <ondrej.ille@gmail.com>
-- Martin Jerabek <martin.jerabek01@gmail.com>
--
-- Project advisors:
-- Jiri Novak <jnovak@fel.cvut.cz>
-- Pavel Pisa <pisa@cmp.felk.cvut.cz>
--
-- Department of Measurement (http://meas.fel.cvut.cz/)
-- Faculty of Electrical Engineering (http://www.fel.cvut.cz)
-- Czech Technical University (http://www.cvut.cz/)
--
-- Permission is hereby granted, free of charge, to any person obtaining a copy
-- of this VHDL component and associated documentation files (the "Component"),
-- to deal in the Component without restriction, including without limitation
-- the rights to use, copy, modify, merge, publish, distribute, sublicense,
-- and/or sell copies of the Component, and to permit persons to whom the
-- Component is furnished to do so, subject to the following conditions:
--
-- The above copyright notice and this permission notice shall be included in
-- all copies or substantial portions of the Component.
--
-- THE COMPONENT IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-- IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-- FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
-- AUTHORS OR COPYRIGHTHOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
-- LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
-- FROM, OUT OF OR IN CONNECTION WITH THE COMPONENT OR THE USE OR OTHER DEALINGS
-- IN THE COMPONENT.
--
-- The CAN protocol is developed by Robert Bosch GmbH and protected by patents.
-- Anybody who wants to implement this IP core on silicon has to obtain a CAN
-- protocol license from Bosch.
--
--------------------------------------------------------------------------------
--------------------------------------------------------------------------------
-- Purpose:
-- Counters for TX and RX frames. Two 32-bit counters are held. Single adder
-- is used and muxed between these two registers since these counters are
-- never supposed to be incremented simultaneously!
--------------------------------------------------------------------------------
-- Revision History:
-- 24.12.2018 Created file
--------------------------------------------------------------------------------
Library ieee;
USE IEEE.std_logic_1164.all;
USE IEEE.numeric_std.ALL;
use work.CANconstants.all;
use work.CANcomponents.ALL;
use work.CAN_FD_frame_format.ALL;
use work.CAN_FD_frame_format.all;
entity bus_traffic_counters is
port(
------------------------------------------------------------------------
-- System clock and Reset
------------------------------------------------------------------------
signal clk_sys :in std_logic;
signal res_n :in std_logic;
-- Clear signals (used as async. reset, not preload to lower resource
-- usage)
signal clear_rx_ctr :in std_logic;
signal clear_tx_ctr :in std_logic;
-- Increment signals (upon sucesfull transmission or reception of frame)
signal inc_tx_ctr :in std_logic;
signal inc_rx_ctr :in std_logic;
-- Counter outputs
signal tx_ctr :out std_logic_vector(31 downto 0);
signal rx_ctr :out std_logic_vector(31 downto 0)
);
end entity;
architecture rtl of bus_traffic_counters is
-- Input selector
signal sel : std_logic;
-- Selected value to increment
signal sel_value : std_logic_vector(31 downto 0);
-- Incremented value by 1
signal inc_value : std_logic_vector(31 downto 0);
begin
-- Input selector
sel <= '1' when (inc_tx_ctr = '1') else
'0';
-- Multiplexor between TX and RX value to increment
sel_value <= tx_ctr when (sel = '1') else
rx_ctr;
-- Incremented value of either TX or RX counter
inc_value <= std_logic_vector(to_unsigned(
to_integer(unsigned(sel_value)) + 1, sel_value'length));
----------------------------------------------------------------------------
-- TX Counter register
----------------------------------------------------------------------------
tx_ctr_proc : process(clk_sys, res_n)
begin
if (res_n = ACT_RESET or clear_tx_ctr = '1') then
tx_ctr <= (OTHERS => '0');
elsif rising_edge(clk_sys) then
if (inc_tx_ctr = '1') then
tx_ctr <= inc_value;
end if;
end if;
end process;
----------------------------------------------------------------------------
-- RX Counter register
----------------------------------------------------------------------------
rx_ctr_proc : process(clk_sys, res_n)
begin
if (res_n = ACT_RESET or clear_rx_ctr = '1') then
rx_ctr <= (OTHERS => '0');
elsif rising_edge(clk_sys) then
if (inc_rx_ctr = '1') then
rx_ctr <= inc_value;
end if;
end if;
end process;
---------------------------------------------------------------------------
-- Assertion that both inputs are not active at the same time since only
-- single adder is used. This would corrupt counter values.
---------------------------------------------------------------------------
assert not (inc_tx_ctr = '1' and inc_rx_ctr = '1') report
"RX frame counter and TX frame counter can't be incremented at once"
severity error;
end architecture;
......@@ -83,6 +83,7 @@
-- Control which sets "int_loop_back_ena" to perform internal
-- loopback upon transmission of DOMINANT bit which should not
-- get to the bus!
-- 24.12.2018 Separated traffic counters to stand-alone component.
--------------------------------------------------------------------------------
Library ieee;
......@@ -1116,31 +1117,17 @@ begin
----------------------------------------------------------------------------
-- Bus traffic measurement
----------------------------------------------------------------------------
bus_tra_proc : process(clk_sys, res_n)
begin
if (res_n = ACT_RESET) then
tx_counter <= (OTHERS => '0');
rx_counter <= (OTHERS => '0');
elsif rising_edge(clk_sys) then
if (drv_clr_rx_ctr = '1') then
rx_counter <= (OTHERS => '0');
elsif (rec_valid = '1') then
rx_counter <= std_logic_vector(to_unsigned(
to_integer(unsigned(rx_counter)) + 1,
rx_counter'length));
end if;
if (drv_clr_tx_ctr = '1') then
tx_counter <= (OTHERS => '0');
elsif (tran_valid = '1') then
tx_counter <= std_logic_vector(to_unsigned(
to_integer(unsigned(tx_counter)) + 1,
tx_counter'length));
end if;
end if;
end process;
bus_traffic_counters_comp : bus_traffic_counters
port map(
clk_sys => clk_sys,
res_n => res_n,
clear_rx_ctr => drv_clr_rx_ctr,
clear_tx_ctr => drv_clr_tx_ctr,
inc_tx_ctr => tran_valid,
inc_rx_ctr => rec_valid,
tx_ctr => tx_counter,
rx_ctr => rx_counter
);
----------------------------------------------------------------------------
......
Markdown is supported
0% or
You are about to add 0 people to the discussion. Proceed with caution.
Finish editing this message first!
Please register or to comment