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Commit 1ac9eeea authored by Ille, Ondrej, Ing.'s avatar Ille, Ondrej, Ing.
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Merge branch '241-align-timestamp-to-64-bit-address' into 'master' 

Resolve "Align TIMESTAMP to 64 bit Address"

Closes #241

See merge request illeondr/CAN_FD_IP_Core!195
parents 3af2fa9f 5d5c1af9
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Showing with 95 additions and 29 deletions
doc/core/registerMap.lyx
View file @ 1ac9eeea
......@@ -262,7 +262,7 @@ Control registers memory region.\end_layout
\noindent
\align center
\begin_inset Tabular
<lyxtabular columns="5" rows="39" version="3">
<lyxtabular columns="5" rows="40" version="3">
<features tabularvalignment="middle">
<column alignment="center" valignment="top" width="3cm">
<column alignment="center" valignment="top" width="3cm">
......@@ -2511,6 +2511,48 @@ hyperref[YOLO_REG]{YOLO\backslash textunderscore REG}\end_layout
<cell alignment="center" leftline="true" multicolumn="1" topline="true" usebox="none" valignment="top">
\begin_inset Text
 
\begin_layout Plain Layout
Reserved\end_layout
\end_inset
</cell>
<cell alignment="center" leftline="true" multicolumn="2" topline="true" usebox="none" valignment="top">
\begin_inset Text
\begin_layout Plain Layout
Reserved\end_layout
\end_inset
</cell>
<cell alignment="center" leftline="true" multicolumn="2" topline="true" usebox="none" valignment="top">
\begin_inset Text
\begin_layout Plain Layout
Reserved\end_layout
\end_inset
</cell>
<cell alignment="center" leftline="true" multicolumn="2" topline="true" usebox="none" valignment="top">
\begin_inset Text
\begin_layout Plain Layout
Reserved\end_layout
\end_inset
</cell>
<cell alignment="center" leftline="true" multicolumn="1" rightline="true" topline="true" usebox="none" valignment="top">
\begin_inset Text
\begin_layout Plain Layout
...\end_layout
\end_inset
</cell>
</row>
<row>
<cell alignment="center" leftline="true" multicolumn="1" topline="true" usebox="none" valignment="top">
\begin_inset Text
\begin_layout Plain Layout
\begin_inset ERT
status open
......@@ -2568,7 +2610,7 @@ hyperref[TIMESTAMP_LOW]{TIMESTAMP\backslash textunderscore LOW}\end_layout
\begin_inset Text
 
\begin_layout Plain Layout
0x8C\end_layout
0x90\end_layout
 
\end_inset
</cell>
......@@ -2634,7 +2676,7 @@ hyperref[TIMESTAMP_HIGH]{TIMESTAMP\backslash textunderscore HIGH}\end_layout
\begin_inset Text
 
\begin_layout Plain Layout
0x90\end_layout
0x94\end_layout
 
\end_inset
</cell>
......@@ -33804,7 +33846,7 @@ label{TIMESTAMP_LOW
Type: read-only
\end_layout
\begin_layout Description
Address: 0x8C
Address: 0x90
\end_layout
\begin_layout Description
Size: 4 bytes
......@@ -34805,7 +34847,7 @@ label{TIMESTAMP_HIGH
Type: read-only
\end_layout
\begin_layout Description
Address: 0x90
Address: 0x94
\end_layout
\begin_layout Description
Size: 4 bytes
......
driver/ctu_can_fd_frame.h
View file @ 1ac9eeea
......@@ -9,8 +9,8 @@
* Martin Jerabek <martin.jerabek01@gmail.com>
*
* Project advisors:
* Jiri Novak <jnovak@fel.cvut.cz>
* Pavel Pisa <pisa@cmp.felk.cvut.cz>
* Jiri Novak <jnovak@fel.cvut.cz>
* Pavel Pisa <pisa@cmp.felk.cvut.cz>
*
* Department of Measurement (http://meas.fel.cvut.cz/)
* Faculty of Electrical Engineering (http://www.fel.cvut.cz)
......
driver/ctu_can_fd_regs.h
View file @ 1ac9eeea
......@@ -9,8 +9,8 @@
* Martin Jerabek <martin.jerabek01@gmail.com>
*
* Project advisors:
* Jiri Novak <jnovak@fel.cvut.cz>
* Pavel Pisa <pisa@cmp.felk.cvut.cz>
* Jiri Novak <jnovak@fel.cvut.cz>
* Pavel Pisa <pisa@cmp.felk.cvut.cz>
*
* Department of Measurement (http://meas.fel.cvut.cz/)
* Faculty of Electrical Engineering (http://www.fel.cvut.cz)
......@@ -87,8 +87,8 @@ enum ctu_can_fd_can_registers {
CTU_CAN_FD_TX_COUNTER = 0x80,
CTU_CAN_FD_DEBUG_REGISTER = 0x84,
CTU_CAN_FD_YOLO_REG = 0x88,
CTU_CAN_FD_TIMESTAMP_LOW = 0x8c,
CTU_CAN_FD_TIMESTAMP_HIGH = 0x90,
CTU_CAN_FD_TIMESTAMP_LOW = 0x90,
CTU_CAN_FD_TIMESTAMP_HIGH = 0x94,
CTU_CAN_FD_TXTB1_DATA_1 = 0x100,
CTU_CAN_FD_TXTB1_DATA_2 = 0x104,
CTU_CAN_FD_TXTB1_DATA_20 = 0x14c,
......
lic/gpl_v2.txt
View file @ 1ac9eeea
......@@ -6,9 +6,9 @@ Authors:
Ondrej Ille <ondrej.ille@gmail.com>
Martin Jerabek <martin.jerabek01@gmail.com>
Project advisors:
Jiri Novak <jnovak@fel.cvut.cz>
Pavel Pisa <pisa@cmp.felk.cvut.cz>
Project advisors:
Jiri Novak <jnovak@fel.cvut.cz>
Pavel Pisa <pisa@cmp.felk.cvut.cz>
Department of Measurement (http://meas.fel.cvut.cz/)
Faculty of Electrical Engineering (http://www.fel.cvut.cz)
......@@ -26,5 +26,6 @@ GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program; if not, write to the Free Software
Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
Foundation, Inc., 51 Franklin Street, Fifth Floor,
Boston, MA 02110-1301, USA.
scripts/license_updater.py
View file @ 1ac9eeea
......@@ -42,6 +42,12 @@ global sup_files
global sub_folders
global lic_text
global USE_KERNEL_LICENSE_FLAG
global KERNEL_LICENSE_FLAG
USE_KERNEL_LICENSE_FLAG = True
KERNEL_LICENSE_FLAG = "// SPDX-License-Identifier: GPL-2.0+"
################################################################################
## Help about the script will be printed to command line
......@@ -75,6 +81,11 @@ def write_license(lic_text, comment_char, file):
# Write the initial line (C)
elif (comment_char == "*"):
# Add kernel License Header
if (USE_KERNEL_LICENSE_FLAG):
file.write(KERNEL_LICENSE_FLAG + "\n");
file.write("/")
for i in range(0, line_length-1):
file.write(comment_char)
......@@ -96,9 +107,11 @@ def write_license(lic_text, comment_char, file):
# Write Begining of the line
if (comment_char == "-" or comment_char == "#"):
file.write(comment_char+comment_char+" ")
elif (comment_char=="*"):
file.write(" "+comment_char+" ")
file.write(comment_char + comment_char + " ")
elif (comment_char == "*"):
file.write(" " + comment_char)
if (len(lic_line.strip()) > 0):
file.write(" ")
# Write Rest of the line
file.write(lic_line)
......@@ -108,8 +121,15 @@ def write_license(lic_text, comment_char, file):
for i in range(0, line_length):
file.write(comment_char)
elif (comment_char=="*"):
for i in range(0, line_length-1):
file.write(comment_char)
if (comment_char == "*"):
file.write(" ")
for i in range(0, line_length-2):
file.write(comment_char)
else:
for i in range(0, line_length-1):
file.write(comment_char)
file.write("/")
file.write("\n")
......
spec/CTU/ip/CAN_FD_IP_Core/2.1/CAN_FD_IP_Core.2.1.xml
View file @ 1ac9eeea
......@@ -1407,7 +1407,7 @@
<ipxact:displayName>TIMESTAMP_HIGH</ipxact:displayName>
<ipxact:description>Register with mirrored values of timestamp input. Bits 63:32 of timestamp input are available from this register. No synchronisation, nor shadowing is implemented on TIMESTAMP_LOW/HIGH registers and user has to take care of proper read from both registers, since overflow of TIMESTAMP_LOW might occur between read of TIMESTAMP_LOW and TIMESTAMP_HIGH.</ipxact:description>
<ipxact:dim>0</ipxact:dim>
<ipxact:addressOffset>'h90</ipxact:addressOffset>
<ipxact:addressOffset>'h94</ipxact:addressOffset>
<ipxact:size>32</ipxact:size>
<ipxact:volatile>true</ipxact:volatile>
<ipxact:access>read-only</ipxact:access>
......@@ -1430,7 +1430,7 @@
<ipxact:displayName>TIMESTAMP_LOW</ipxact:displayName>
<ipxact:description>Register with mirrored values of timestamp input. Bits 31:0 of timestamp input are available from this register. No synchronisation, nor shadowing is implemented on TIMESTAMP_LOW/HIGH registers and user has to take care of proper read from both registers, since overflow of TIMESTAMP_LOW might occur between read of TIMESTAMP_LOW and TIMESTAMP_HIGH.</ipxact:description>
<ipxact:dim>0</ipxact:dim>
<ipxact:addressOffset>'h8C</ipxact:addressOffset>
<ipxact:addressOffset>'h90</ipxact:addressOffset>
<ipxact:size>32</ipxact:size>
<ipxact:volatile>true</ipxact:volatile>
<ipxact:access>read-only</ipxact:access>
......
src/lib/can_fd_register_map.vhd
View file @ 1ac9eeea
......@@ -103,8 +103,8 @@ package can_fd_register_map is
constant TX_COUNTER_ADR : std_logic_vector(11 downto 0) := x"080";
constant DEBUG_REGISTER_ADR : std_logic_vector(11 downto 0) := x"084";
constant YOLO_REG_ADR : std_logic_vector(11 downto 0) := x"088";
constant TIMESTAMP_LOW_ADR : std_logic_vector(11 downto 0) := x"08C";
constant TIMESTAMP_HIGH_ADR : std_logic_vector(11 downto 0) := x"090";
constant TIMESTAMP_LOW_ADR : std_logic_vector(11 downto 0) := x"090";
constant TIMESTAMP_HIGH_ADR : std_logic_vector(11 downto 0) := x"094";
------------------------------------------------------------------------------
------------------------------------------------------------------------------
......
src/memory_registers/generated/control_registers_reg_map.vhd
View file @ 1ac9eeea
......@@ -82,8 +82,8 @@ end entity control_registers_reg_map;
architecture rtl of control_registers_reg_map is
signal reg_sel : std_logic_vector(36 downto 0);
constant ADDR_VECT
: std_logic_vector(221 downto 0) := "100100100011100010100001100000011111011110011101011100011011011010011001011000010111010110010101010100010011010010010001010000001111001110001101001100001011001010001001001000000111000110000101000100000011000010000001000000";
signal read_data_mux_in : std_logic_vector(1183 downto 0);
: std_logic_vector(221 downto 0) := "100101100100100010100001100000011111011110011101011100011011011010011001011000010111010110010101010100010011010010010001010000001111001110001101001100001011001010001001001000000111000110000101000100000011000010000001000000";
signal read_data_mux_in : std_logic_vector(1215 downto 0);
signal read_data_mask_n : std_logic_vector(31 downto 0);
signal control_registers_out_i : Control_registers_out_t;
signal read_mux_ena : std_logic;
......@@ -779,7 +779,7 @@ begin
data_mux_control_registers_comp : data_mux
generic map(
data_out_width => 32 ,
data_in_width => 1184 ,
data_in_width => 1216 ,
sel_width => 6 ,
registered_out => REGISTERED_READ ,
reset_polarity => RESET_POLARITY
......@@ -798,12 +798,15 @@ begin
-- Read data driver
------------------------------------------------------------------------------
read_data_mux_in <=
-- Adress:144
-- Adress:148
control_registers_in.timestamp_high &
-- Adress:140
-- Adress:144
control_registers_in.timestamp_low &
-- Adress:140
"00000000" & "00000000" & "00000000" & "00000000" &
-- Adress:136
control_registers_in.yolo_reg &
......
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