Commit 1a5ce724 authored by Ille, Ondrej, Ing.'s avatar Ille, Ondrej, Ing.

test: Add ERR_CAPT form error feature test.

parent da60ec58
--------------------------------------------------------------------------------
--
-- CTU CAN FD IP Core
-- Copyright (C) 2015-2018
--
-- Authors:
-- Ondrej Ille <ondrej.ille@gmail.com>
-- Martin Jerabek <martin.jerabek01@gmail.com>
--
-- Project advisors:
-- Jiri Novak <jnovak@fel.cvut.cz>
-- Pavel Pisa <pisa@cmp.felk.cvut.cz>
--
-- Department of Measurement (http://meas.fel.cvut.cz/)
-- Faculty of Electrical Engineering (http://www.fel.cvut.cz)
-- Czech Technical University (http://www.cvut.cz/)
--
-- Permission is hereby granted, free of charge, to any person obtaining a copy
-- of this VHDL component and associated documentation files (the "Component"),
-- to deal in the Component without restriction, including without limitation
-- the rights to use, copy, modify, merge, publish, distribute, sublicense,
-- and/or sell copies of the Component, and to permit persons to whom the
-- Component is furnished to do so, subject to the following conditions:
--
-- The above copyright notice and this permission notice shall be included in
-- all copies or substantial portions of the Component.
--
-- THE COMPONENT IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-- IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-- FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
-- AUTHORS OR COPYRIGHTHOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
-- LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
-- FROM, OUT OF OR IN CONNECTION WITH THE COMPONENT OR THE USE OR OTHER DEALINGS
-- IN THE COMPONENT.
--
-- The CAN protocol is developed by Robert Bosch GmbH and protected by patents.
-- Anybody who wants to implement this IP core on silicon has to obtain a CAN
-- protocol license from Bosch.
--
--------------------------------------------------------------------------------
--------------------------------------------------------------------------------
-- @TestInfoStart
--
-- @Purpose:
-- ERR_CAPT[ERR_POS] = ERC_POS_ERR, Error code capture in Error frame feature
-- test.
--
-- @Verifies:
-- @1. Value of ERR_CAPT register when Error is detected inside Error frame.
--
-- @Test sequence:
-- @1. Check that ERR_CAPT contains no error (post reset).
-- @2. Set Node 2 to ACK forbidden mode. Generate random frame and send it by
-- Node 1. Wait until error frame is transmitted by Node 1. Wait for
-- random amount of bits (0-5) and force bus to Recessive. Wait until
-- sample point and check value of Error code capture in Node 1.
--
-- @TestInfoEnd
--------------------------------------------------------------------------------
-- Revision History:
-- 12.01.2020 Created file
--------------------------------------------------------------------------------
context work.ctu_can_synth_context;
context work.ctu_can_test_context;
use lib.pkg_feature_exec_dispath.all;
package err_capt_err_frm_feature is
procedure err_capt_err_frm_feature_exec(
signal so : out feature_signal_outputs_t;
signal rand_ctr : inout natural range 0 to RAND_POOL_SIZE;
signal iout : in instance_outputs_arr_t;
signal mem_bus : inout mem_bus_arr_t;
signal bus_level : in std_logic
);
end package;
package body err_capt_err_frm_feature is
procedure err_capt_err_frm_feature_exec(
signal so : out feature_signal_outputs_t;
signal rand_ctr : inout natural range 0 to RAND_POOL_SIZE;
signal iout : in instance_outputs_arr_t;
signal mem_bus : inout mem_bus_arr_t;
signal bus_level : in std_logic
) is
variable ID_1 : natural := 1;
variable ID_2 : natural := 2;
-- Generated frames
variable frame_1 : SW_CAN_frame_type;
-- Node status
variable stat_1 : SW_status;
variable wait_time : natural;
variable frame_sent : boolean;
variable err_capt : SW_error_capture;
variable mode_2 : SW_mode;
begin
-----------------------------------------------------------------------
-- @1. Check that ERR_CAPT contains no error (post reset).
-----------------------------------------------------------------------
info("Step 1");
CAN_read_error_code_capture(err_capt, ID_1, mem_bus(1));
check(err_capt.err_pos = err_pos_other, "Reset of ERR_CAPT!");
-----------------------------------------------------------------------
-- @2. Set Node 2 to ACK forbidden mode. Generate random frame and send
-- it by Node 1. Wait until error frame is transmitted by Node 1.
-- Wait for random amount of bits (0-5) and force bus to Recessive.
-- Wait until sample point and check value of Error code capture in
-- Node 1.
-----------------------------------------------------------------------
mode_2.acknowledge_forbidden := true;
set_core_mode(mode_2, ID_2, mem_bus(2));
CAN_generate_frame(rand_ctr, frame_1);
CAN_send_frame(frame_1, 1, ID_1, mem_bus(1), frame_sent);
CAN_wait_error_frame(ID_1, mem_bus(1));
rand_int_v(rand_ctr, 5, wait_time);
for i in 1 to wait_time loop
CAN_wait_sample_point(iout(1).stat_bus);
end loop;
wait for 20 ns;
force_bus_level(RECESSIVE, so.bl_force, so.bl_inject);
CAN_wait_sample_point(iout(1).stat_bus, false);
wait for 20 ns; -- To be sure that opposite bit is sampled!
release_bus_level(so.bl_force);
CAN_read_error_code_capture(err_capt, ID_1, mem_bus(1));
check(err_capt.err_type = can_err_bit, "Bit error detected!");
check(err_capt.err_pos = err_pos_err_frame,
"Error detected in Error frame!");
wait for 100 ns; -- For debug only to see waves properly!
end procedure;
end package body;
......@@ -71,6 +71,7 @@ feature:
err_capt_ctrl_form:
err_capt_data_bit:
err_capt_eof:
err_capt_err_frm:
err_capt_sof:
err_norm_fd:
error_rules_a:
......
......@@ -102,6 +102,7 @@ feature:
err_capt_ctrl_form:
err_capt_data_bit:
err_capt_eof:
err_capt_err_frm:
err_capt_sof:
err_norm_fd:
iterations: 5
......
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