Commit 19e75e47 authored by Ille, Ondrej, Ing.'s avatar Ille, Ondrej, Ing.

src: Resolve warnings from Vivado synthesis.

parent e8bf93bf
Pipeline #17568 passed with stages
in 20 minutes and 53 seconds
......@@ -976,7 +976,6 @@ begin
err_frm_req => err_frm_req, -- IN
is_err_active => is_err_active, -- IN
bst_ctr => bst_ctr, -- IN
tran_word => tran_word, -- IN
tran_identifier => tran_identifier, -- IN
tran_word_swapped => tran_word_swapped, -- IN
tran_dlc => tran_dlc -- IN
......
......@@ -1306,8 +1306,8 @@ begin
is_receiver, crc_match, drv_ack_forb, drv_self_test_ena, tx_frame_ready,
go_to_suspend, frame_start, ctrl_ctr_one, drv_bus_off_reset_q,
reinteg_ctr_expired, first_err_delim_q, go_to_stuff_count,
crc_length_i, data_length_bits_c, ctrl_ctr_mem_index, is_bus_off
)
crc_length_i, data_length_bits_c, ctrl_ctr_mem_index, is_bus_off,
block_txtb_unlock)
begin
-----------------------------------------------------------------------
......
......@@ -156,9 +156,6 @@ entity tx_shift_reg is
-----------------------------------------------------------------------
-- TXT Buffers interface
-----------------------------------------------------------------------
-- TXT Buffer RAM word
tran_word :in std_logic_vector(31 downto 0);
-- TX Identifier
tran_identifier :in std_logic_vector(28 downto 0);
......
......@@ -674,7 +674,6 @@ begin
txtb_ptr => txtb_ptr, -- IN
-- Memory registers interface
drv_bus => drv_bus, -- IN
txtb_prorities => txtb_prorities, -- IN
timestamp => timestamp -- IN
);
......
......@@ -2546,9 +2546,6 @@ package can_components is
-----------------------------------------------------------------------
-- TXT Buffers interface
-----------------------------------------------------------------------
-- TXT Buffer RAM word
tran_word :in std_logic_vector(31 downto 0);
-- TX Identifier
tran_identifier :in std_logic_vector(28 downto 0);
......@@ -3690,9 +3687,6 @@ package can_components is
-- Sync Trigger Request (TX Trigger request)
tx_trig_req : in std_logic;
-- Sample control (Nominal, Data, Secondary)
sp_control : in std_logic_vector(1 downto 0);
-----------------------------------------------------------------------
-- Trigger outputs
-----------------------------------------------------------------------
......@@ -3810,12 +3804,6 @@ package can_components is
-- RX Buffer RAM is being read by SW
read_increment :in std_logic;
-----------------------------------------------------------------------
-- Memory registers interface
-----------------------------------------------------------------------
-- Driving bus
drv_bus :in std_logic_vector(1023 downto 0);
-----------------------------------------------------------------------
-- Status outputs
-----------------------------------------------------------------------
......@@ -4174,9 +4162,6 @@ package can_components is
-----------------------------------------------------------------------
-- Memory registers interface
-----------------------------------------------------------------------
-- Driving Bus
drv_bus :in std_logic_vector(1023 downto 0);
-- Priorities of TXT Buffers
txtb_prorities :in t_txt_bufs_priorities;
......
......@@ -466,8 +466,7 @@ begin
res_n => res_n, -- IN
rx_trig_req => rx_trig_req, -- IN
tx_trig_req => tx_trig_req, -- IN
sp_control => sp_control, -- IN
rx_triggers => rx_triggers, -- OUT
tx_trigger => tx_trigger -- OUT
);
......
......@@ -120,9 +120,6 @@ entity trigger_generator is
-- TX Trigger request (Sync)
tx_trig_req : in std_logic;
-- Sample control (Nominal, Data, Secondary)
sp_control : in std_logic_vector(1 downto 0);
-----------------------------------------------------------------------
-- Trigger outputs
-----------------------------------------------------------------------
......
......@@ -466,7 +466,6 @@ begin
store_ts_wr_ptr => store_ts_wr_ptr, -- IN
inc_ts_wr_ptr => inc_ts_wr_ptr, -- IN
read_increment => read_increment, -- IN
drv_bus => drv_bus, -- IN
read_pointer => read_pointer, -- OUT
read_pointer_inc_1 => read_pointer_inc_1, -- OUT
......
......@@ -118,12 +118,6 @@ entity rx_buffer_pointers is
-- RX Buffer RAM is being read by SW
read_increment :in std_logic;
-----------------------------------------------------------------------
-- Memory registers interface
-----------------------------------------------------------------------
-- Driving bus
drv_bus :in std_logic_vector(1023 downto 0);
-----------------------------------------------------------------------
-- Status outputs
-----------------------------------------------------------------------
......
......@@ -143,9 +143,6 @@ entity tx_arbitrator is
-----------------------------------------------------------------------
-- Memory registers interface
-----------------------------------------------------------------------
-- Driving Bus
drv_bus :in std_logic_vector(1023 downto 0);
-- Priorities of TXT Buffers
txtb_prorities :in t_txt_bufs_priorities;
......
......@@ -90,7 +90,6 @@ architecture tx_arb_unit_test of CAN_test is
signal txtb_changed : std_logic;
signal txtb_hw_cmd_index : natural range 0 to C_TXT_BUFFER_COUNT - 1;
signal txtb_ptr : natural range 0 to 19 := 0;
signal drv_bus : std_logic_vector(1023 downto 0);
signal txtb_prorities : t_txt_bufs_priorities :=
(OTHERS => (OTHERS => '0'));
signal timestamp : std_logic_vector(63 downto 0) :=
......@@ -217,7 +216,6 @@ begin
txtb_changed => txtb_changed,
txtb_hw_cmd_index => txtb_hw_cmd_index,
txtb_ptr => txtb_ptr,
drv_bus => drv_bus,
txtb_prorities => txtb_prorities,
timestamp => timestamp
);
......
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