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Commit 18acb948 authored by Ille, Ondrej, Ing.'s avatar Ille, Ondrej, Ing.
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Brought up Invalid configs feature test.

parent 06926288
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test/feature/invalid_configs_feature_tb.vhd
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......@@ -37,13 +37,16 @@
--------------------------------------------------------------------------------
-- Purpose:
-- Feature test for frame transmittion with invalid configurations
-- Feature test for frame transmittion with invalid combination of configu
-- rations.
--
--------------------------------------------------------------------------------
-- Revision History:
--
-- 30.6.2016 Created file
-- 06.02.2018 Modified to work with the IP-XACT generated memory map
-- 12.6.2018 Modified to use CAN Test lib instead of direct register
-- access functions.
--------------------------------------------------------------------------------
Library ieee;
......@@ -59,112 +62,97 @@ use work.CAN_FD_frame_format.all;
package invalid_config_feature is
procedure invalid_config_feature_exec(
variable outcome : inout boolean;
signal rand_ctr :inout natural range 0 to RAND_POOL_SIZE;
signal mem_bus_1 :inout Avalon_mem_type;
signal mem_bus_2 :inout Avalon_mem_type;
--Additional signals for tests
--Pretty much everything can be read out of stat bus...
signal bus_level :in std_logic;
signal drv_bus_1 :in std_logic_vector(1023 downto 0);
signal drv_bus_2 :in std_logic_vector(1023 downto 0);
signal stat_bus_1 :in std_logic_vector(511 downto 0);
signal stat_bus_2 :in std_logic_vector(511 downto 0)
);
procedure invalid_config_feature_exec(
variable outcome : inout boolean;
signal rand_ctr : inout natural range 0 to RAND_POOL_SIZE;
signal mem_bus_1 : inout Avalon_mem_type;
signal mem_bus_2 : inout Avalon_mem_type;
signal bus_level : in std_logic;
signal drv_bus_1 : in std_logic_vector(1023 downto 0);
signal drv_bus_2 : in std_logic_vector(1023 downto 0);
signal stat_bus_1 : in std_logic_vector(511 downto 0);
signal stat_bus_2 : in std_logic_vector(511 downto 0)
);
end package;
package body invalid_config_feature is
procedure invalid_config_feature_exec(
variable outcome : inout boolean;
signal rand_ctr :inout natural range 0 to RAND_POOL_SIZE;
signal mem_bus_1 :inout Avalon_mem_type;
signal mem_bus_2 :inout Avalon_mem_type;
--Additional signals for tests
--Pretty much everything can be read out of stat bus...
signal bus_level :in std_logic;
signal drv_bus_1 :in std_logic_vector(1023 downto 0);
signal drv_bus_2 :in std_logic_vector(1023 downto 0);
signal stat_bus_1 :in std_logic_vector(511 downto 0);
signal stat_bus_2 :in std_logic_vector(511 downto 0)
)is
variable r_data : std_logic_vector(31 downto 0):=(OTHERS => '0');
variable CAN_frame : SW_CAN_frame_type;
variable frame_sent : boolean:=false;
variable ctr_1 : natural;
variable ctr_2 : natural;
variable ID_1 : natural:=1;
variable ID_2 : natural:=2;
begin
outcome:=true;
---------
--Part 1
---------
-----------------------------------------------
--Release recieve buffer 2
-----------------------------------------------
CAN_read(r_data,MODE_ADR,ID_2,mem_bus_2);
r_data(RRB_IND) := '1';
CAN_write(r_data,MODE_ADR,ID_2,mem_bus_2);
-----------------------------------------------
--Send NORMAL frame with BRS=1
-----------------------------------------------
CAN_generate_frame(rand_ctr,CAN_frame);
CAN_frame.frame_format:= NORMAL_CAN;
CAN_frame.brs:=BR_SHIFT;
CAN_send_frame(CAN_frame,1,ID_1,mem_bus_1,frame_sent);
CAN_wait_frame_sent(ID_1,mem_bus_1);
-----------------------------------------------
-- Read the frame format word
-- Detection of FD frame or Bit rate shift bit
-- is considered to be and error
-----------------------------------------------
CAN_read(r_data,RX_DATA_ADR,ID_2,mem_bus_2);
if(r_data(FR_TYPE_IND) /= '0' or r_data(BRS_IND) /= '0') then
outcome:= false;
end if;
---------
--Part 2
---------
-----------------------------------------------
--Release recieve buffer 2
-----------------------------------------------
CAN_read(r_data,MODE_ADR,ID_2,mem_bus_2);
r_data(RRB_IND) := '1';
CAN_write(r_data,MODE_ADR,ID_2,mem_bus_2);
-----------------------------------------------
--Send FD frame with RTR=1
-----------------------------------------------
CAN_generate_frame(rand_ctr,CAN_frame);
CAN_frame.frame_format:= FD_CAN;
CAN_frame.rtr:=RTR_FRAME;
CAN_send_frame(CAN_frame,1,ID_1,mem_bus_1,frame_sent);
CAN_wait_frame_sent(ID_1,mem_bus_1);
-----------------------------------------------
-- Read the frame format word
-----------------------------------------------
CAN_read(r_data,RX_DATA_ADR,ID_2,mem_bus_2);
if(r_data(FR_TYPE_IND) /= FD_CAN or r_data(RTR_IND) /= NO_RTR_FRAME) then
outcome:= false;
end if;
procedure invalid_config_feature_exec(
variable outcome : inout boolean;
signal rand_ctr : inout natural range 0 to RAND_POOL_SIZE;
signal mem_bus_1 : inout Avalon_mem_type;
signal mem_bus_2 : inout Avalon_mem_type;
signal bus_level : in std_logic;
signal drv_bus_1 : in std_logic_vector(1023 downto 0);
signal drv_bus_2 : in std_logic_vector(1023 downto 0);
signal stat_bus_1 : in std_logic_vector(511 downto 0);
signal stat_bus_2 : in std_logic_vector(511 downto 0)
)is
variable tx_frame : SW_CAN_frame_type;
variable rx_frame : SW_CAN_frame_type;
variable frame_sent : boolean := false;
variable ID_1 : natural := 1;
variable ID_2 : natural := 2;
variable command : SW_command;
begin
outcome := true;
------------------------------------------------------------------------
-- Part 1
------------------------------------------------------------------------
------------------------------------------------------------------------
-- Release recieve buffer 2
------------------------------------------------------------------------
command.release_rec_buffer := true;
give_controller_command(command, ID_2, mem_bus_2);
command.release_rec_buffer := false;
------------------------------------------------------------------------
-- Send NORMAL frame with BRS = 1
------------------------------------------------------------------------
CAN_generate_frame(rand_ctr, tx_frame);
tx_frame.frame_format := NORMAL_CAN;
tx_frame.brs := BR_SHIFT;
CAN_send_frame(tx_frame, 1, ID_1, mem_bus_1, frame_sent);
CAN_wait_frame_sent(ID_1, mem_bus_1);
------------------------------------------------------------------------
-- Read frame. CAN 2.0 frame with no BRS bit should be received.
------------------------------------------------------------------------
CAN_read_frame(rx_frame, ID_2, mem_bus_2);
if (rx_frame.brs = BR_SHIFT or rx_frame.frame_format = FD_CAN) then
outcome := false;
end if;
------------------------------------------------------------------------
-- Part 2
------------------------------------------------------------------------
------------------------------------------------------------------------
-- Release recieve buffer 2
------------------------------------------------------------------------
give_controller_command(command, ID_2, mem_bus_2);
------------------------------------------------------------------------
-- Send FD frame with RTR = 1
------------------------------------------------------------------------
CAN_generate_frame(rand_ctr, tx_frame);
tx_frame.frame_format := FD_CAN;
tx_frame.rtr := RTR_FRAME;
CAN_send_frame(tx_frame, 1, ID_1, mem_bus_1, frame_sent);
CAN_wait_frame_sent(ID_1, mem_bus_1);
------------------------------------------------------------------------
-- Read frame. CAN FD Frame without RTR bit should be read
------------------------------------------------------------------------
CAN_read_frame(rx_frame, ID_2, mem_bus_2);
if (rx_frame.frame_format = NORMAL_CAN or rx_frame.rtr = RTR_FRAME) then
outcome := false;
end if;
end procedure;
end procedure;
end package body;
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