From 18679c5683a2862f7cf6f451f9769b09b7c4c14e Mon Sep 17 00:00:00 2001
From: "Ille, Ondrej, Ing" <illeondr@fel.cvut.cz>
Date: Fri, 29 Jun 2018 15:23:42 +0200
Subject: [PATCH] Formatted reset synchroniser.

---
 src/rst_sync.vhd | 32 ++++++++++++++++----------------
 1 file changed, 16 insertions(+), 16 deletions(-)

diff --git a/src/rst_sync.vhd b/src/rst_sync.vhd
index 3ce8c6ec..19d27184 100644
--- a/src/rst_sync.vhd
+++ b/src/rst_sync.vhd
@@ -48,24 +48,24 @@ Library ieee;
 use ieee.std_logic_1164.all;
 
 entity rst_sync is
-  port (
-      signal clk    : in  std_logic;
-      signal arst_n : in  std_logic;
-      signal rst_n  : out std_logic
-  );
+    port (
+        signal clk      : in    std_logic;
+        signal arst_n   : in    std_logic;
+        signal rst_n    : out   std_logic
+    );
 end rst_sync;
 
 architecture rtl of rst_sync is
-  signal rff : std_logic; 	
+    signal rff          :       std_logic; 	
 begin
- process (clk, arst_n)
- begin
-  if (arst_n = '0') then
-    rff <= '0';
-    rst_n <= '0';
-  elsif (rising_edge(clk)) then
-    rff <= '1';
-    rst_n <= rff;
-  end if;
- end process;
+    process (clk, arst_n)
+    begin
+        if (arst_n = '0') then
+            rff     <= '0';
+            rst_n   <= '0';
+        elsif (rising_edge(clk)) then
+            rff     <= '1';
+            rst_n   <= rff;
+        end if;
+    end process;
 end rtl;
-- 
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