Merge branch '125-consolidate-test-library' into 'master'

Resolve "Consolidate test library"

Closes #125

See merge request illeondr/CAN_FD_IP_Core!65

test/sanity/sanity_config.tcl

@@ -42,7 +42,7 @@ quietly set SAN_CFG [ list  [ list star 10 10 10 10 0.0 0.0 \
 									10 10 10 10 \
 									0 5 10 15 \
 									70.0 5.0 300000.0 100000.0 \
-									4 1 8 8 8 3 3 1 5 2 \
+									4 1 8 8 8 4 3 1 5 2 \
 									"1Mb/10Mb 20 m Star" 5
 							] 
 							##[ list star 10 10 10 10 0.0 0.0 \

test/unit/Bit_Stuffing/Bit_Stuffing_tb.vhd

@@ -191,13 +191,13 @@ begin
         rx_trig = '0' and err_data = '0') then
       if (rand_val > 0.95) then
         
-        rand_logic(rand_set_ctr, bs_enable, 0.9);
+        rand_logic_s(rand_set_ctr, bs_enable, 0.9);
         wait for 0 ns;
         bd_enable <= bs_enable;
         
-        rand_logic(rand_set_ctr, fixed_stuff, 0.25);
+        rand_logic_s(rand_set_ctr, fixed_stuff, 0.25);
         
-        rand_logic_vect(rand_set_ctr, bs_length, 0.2);
+        rand_logic_vect_s(rand_set_ctr, bs_length, 0.2);
         wait for 0 ns;
 	
         -- Bit Stuffing of 0,1 or 2 is not needed.
@@ -220,7 +220,7 @@ begin
   begin
     wait until rising_edge(tx_trig) and data_halt = '0' and 
 		stuff_error = '0' and err_data = '0';
-    rand_logic(rand_tx_ctr, tx_data, 0.5);
+    rand_logic_s(rand_tx_ctr, tx_data, 0.5);
   end process;
   
   --------------------------------

test/unit/Bus_Sampling/Bus_Sync_tb.vhd

@@ -211,7 +211,7 @@ begin
     if (generate_ones = true) then
       data_tx <= RECESSIVE;
     else
-      rand_logic(rand_ctr_data_gen, data_tx, 0.5);
+      rand_logic_s(rand_ctr_data_gen, data_tx, 0.5);
     end if;
     
   end process;

test/unit/CRC/CRC_tb.vhd

@@ -320,7 +320,7 @@ begin
       log("Starting loop nr " & integer'image(loop_ctr), info_l, log_level);
       
       --Generate random ISO, non ISO
-      rand_logic(rand_ctr, drv_fd_type, 0.5);
+      rand_logic_s(rand_ctr, drv_fd_type, 0.5);
       
       --Generate bit sequence
       log("Generating random bit sequence", info_l,  log_level);

test/unit/Evnt_Logger/Event_logger_tb.vhd

@@ -203,7 +203,7 @@ begin
   variable rand_val:real:=0.0;
   begin
     wait until falling_edge(clk_sys);
-    rand_logic_vect(rand_ctr_2,stat_bus_short,0.1);
+    rand_logic_vect_s(rand_ctr_2,stat_bus_short,0.1);
         
         
     --Here we emulate frame
@@ -227,8 +227,8 @@ begin
       PC_State  <=  sof;
     end if;
     
-    rand_logic(rand_ctr_2,data_overrun,0.2);
-    rand_logic(rand_ctr_2,sync_edge,0.2);  
+    rand_logic_s(rand_ctr_2,data_overrun,0.2);
+    rand_logic_s(rand_ctr_2,sync_edge,0.2);  
       
     rand_real_v(rand_ctr_2,rand_val);
     wt:= integer(rand_val*100.0) * 1 ns;

test/unit/Int_Manager/Int_Manager_tb.vhd

@@ -199,81 +199,81 @@ architecture int_man_unit_test of CAN_test is
     )is
     begin
       if (error_valid = '1') then
-        rand_logic(rand_ctr, error_valid, 0.85);
+        rand_logic_s(rand_ctr, error_valid, 0.85);
       else
-        rand_logic(rand_ctr, error_valid, 0.1);
+        rand_logic_s(rand_ctr, error_valid, 0.1);
       end if;
       
       if (error_passive_changed = '1') then
-        rand_logic(rand_ctr, error_passive_changed, 0.85);
+        rand_logic_s(rand_ctr, error_passive_changed, 0.85);
       else
-        rand_logic(rand_ctr, error_passive_changed, 0.05);
+        rand_logic_s(rand_ctr, error_passive_changed, 0.05);
       end if;
       
       if (error_warning_limit = '1') then
-        rand_logic(rand_ctr, error_warning_limit, 0.85);
+        rand_logic_s(rand_ctr, error_warning_limit, 0.85);
       else
-        rand_logic(rand_ctr, error_warning_limit, 0.05);
+        rand_logic_s(rand_ctr, error_warning_limit, 0.05);
       end if;
       
       if (arbitration_lost = '1') then
-        rand_logic(rand_ctr, arbitration_lost, 0.95);
+        rand_logic_s(rand_ctr, arbitration_lost, 0.95);
       else
-        rand_logic(rand_ctr, arbitration_lost, 0.05);
+        rand_logic_s(rand_ctr, arbitration_lost, 0.05);
       end if;
       
       if (tx_finished = '1') then
-        rand_logic(rand_ctr, tx_finished, 0.95);
+        rand_logic_s(rand_ctr, tx_finished, 0.95);
       else
-        rand_logic(rand_ctr, tx_finished, 0.05);
+        rand_logic_s(rand_ctr, tx_finished, 0.05);
       end if;
       
       if (br_shifted = '1') then
-        rand_logic(rand_ctr, br_shifted, 0.95);
+        rand_logic_s(rand_ctr, br_shifted, 0.95);
       else
-        rand_logic(rand_ctr, br_shifted, 0.05);
+        rand_logic_s(rand_ctr, br_shifted, 0.05);
       end if;
       
       if (rx_message_disc = '1') then
-        rand_logic(rand_ctr, rx_message_disc, 0.95);
+        rand_logic_s(rand_ctr, rx_message_disc, 0.95);
       else
-        rand_logic(rand_ctr, rx_message_disc, 0.05);
+        rand_logic_s(rand_ctr, rx_message_disc, 0.05);
       end if;
       
       if (rec_message_valid = '1') then
-        rand_logic(rand_ctr, rec_message_valid, 0.95);
+        rand_logic_s(rand_ctr, rec_message_valid, 0.95);
       else
-        rand_logic(rand_ctr, rec_message_valid, 0.05);
+        rand_logic_s(rand_ctr, rec_message_valid, 0.05);
       end if;
       
       if (rx_full = '1') then
-        rand_logic(rand_ctr, rx_full, 0.95);
+        rand_logic_s(rand_ctr, rx_full, 0.95);
       else
-        rand_logic(rand_ctr, rx_full, 0.05);
+        rand_logic_s(rand_ctr, rx_full, 0.05);
       end if;
       
       if (loger_finished = '1') then
-        rand_logic(rand_ctr, loger_finished, 0.95);
+        rand_logic_s(rand_ctr, loger_finished, 0.95);
       else
-        rand_logic(rand_ctr, loger_finished, 0.05);
+        rand_logic_s(rand_ctr, loger_finished, 0.05);
       end if;
       
       if (rx_empty = '0') then
-        rand_logic(rand_ctr, rx_empty, 0.95);
+        rand_logic_s(rand_ctr, rx_empty, 0.95);
       else
-        rand_logic(rand_ctr, rx_empty, 0.05);
+        rand_logic_s(rand_ctr, rx_empty, 0.05);
       end if;
 
       if (txt_hw_cmd.lock = '1') then
-        rand_logic(rand_ctr, txt_hw_cmd.lock, 0.95);
+        rand_logic_s(rand_ctr, txt_hw_cmd.lock, 0.95);
       else
-        rand_logic(rand_ctr, txt_hw_cmd.lock, 0.05);
+        rand_logic_s(rand_ctr, txt_hw_cmd.lock, 0.05);
       end if;
 
       if (txt_hw_cmd.lock = '1') then
-        rand_logic(rand_ctr, txt_hw_cmd.unlock, 0.95);
+        rand_logic_s(rand_ctr, txt_hw_cmd.unlock, 0.95);
       else
-        rand_logic(rand_ctr, txt_hw_cmd.unlock, 0.05);
+        rand_logic_s(rand_ctr, txt_hw_cmd.unlock, 0.05);
       end if;
       
     end procedure;    
@@ -305,19 +305,19 @@ architecture int_man_unit_test of CAN_test is
         -- Only one command is generated at any time, since commands are
         -- coming from different registers!
         if (tmp < 0.2) then
-            rand_logic_vect(rand_ctr, drv_int_clear, 0.4);
+            rand_logic_vect_s(rand_ctr, drv_int_clear, 0.4);
         
         elsif (tmp < 0.4) then
-            rand_logic_vect(rand_ctr, drv_int_ena_set, 0.2);
+            rand_logic_vect_s(rand_ctr, drv_int_ena_set, 0.2);
 
         elsif (tmp < 0.6) then
-            rand_logic_vect(rand_ctr, drv_int_ena_clear, 0.4);
+            rand_logic_vect_s(rand_ctr, drv_int_ena_clear, 0.4);
 
         elsif (tmp < 0.8) then
-            rand_logic_vect(rand_ctr, drv_int_mask_set, 0.2);
+            rand_logic_vect_s(rand_ctr, drv_int_mask_set, 0.2);
 
         else
-            rand_logic_vect(rand_ctr, drv_int_mask_clear, 0.4);
+            rand_logic_vect_s(rand_ctr, drv_int_mask_clear, 0.4);
         end if;
 
         wait for 0 ns;