Commit 151488aa authored by Ille, Ondrej, Ing.'s avatar Ille, Ondrej, Ing.

src: Remove ack_received signal as this is not used!

parent 339a0656
Pipeline #19084 passed with stages
in 21 minutes and 33 seconds
......@@ -366,7 +366,6 @@ architecture rtl of can_core is
signal tran_delay_meas_i : std_logic;
signal tran_valid_i : std_logic;
signal rec_valid_i : std_logic;
signal ack_received_i : std_logic;
signal br_shifted_i : std_logic;
-- Fault confinement status signals
......@@ -586,7 +585,6 @@ begin
decrement_rec => decrement_rec, -- OUT
-- Status signals
ack_received => ack_received_i, -- OUT
br_shifted => br_shifted_i, -- OUT
form_err => form_err, -- OUT
ack_err => ack_err, -- OUT
......@@ -900,6 +898,7 @@ begin
stat_bus(113) <= '0';
stat_bus(115) <= '0';
stat_bus(183) <= '0';
stat_bus(255) <= '0';
stat_bus(120 downto 118) <= (OTHERS => '0');
stat_bus(178 downto 158) <= (OTHERS => '0');
......@@ -1134,9 +1133,6 @@ begin
stat_bus(STAT_ERR_VALID_INDEX) <=
err_detected_i;
stat_bus(STAT_ACK_RECIEVED_OUT_INDEX) <=
ack_received_i;
stat_bus(STAT_BIT_ERR_VALID_INDEX) <=
bit_err;
......
......@@ -400,9 +400,6 @@ entity protocol_control is
-----------------------------------------------------------------------
-- Status signals
-----------------------------------------------------------------------
-- ACK received
ack_received :out std_logic;
-- Bit rate shifted
br_shifted :out std_logic;
......@@ -803,7 +800,6 @@ begin
ssp_reset => ssp_reset, -- OUT
tran_delay_meas => tran_delay_meas, -- OUT
tran_valid => tran_valid, -- OUT
ack_received => ack_received, -- OUT
crc_enable => crc_enable, -- OUT
crc_spec_enable => crc_spec_enable, -- OUT
crc_calc_from_rx => crc_calc_from_rx, -- OUT
......
......@@ -500,9 +500,6 @@ entity protocol_control_fsm is
-- Transmitted frame is valid
tran_valid :out std_logic;
-- ACK received
ack_received :out std_logic;
-- CRC calculation enabled
crc_enable :out std_logic;
......@@ -1405,7 +1402,6 @@ begin
set_err_active_i <= '0';
br_shifted_i <= '0';
ack_received <= '0';
-- Bit Stuffing/Destuffing control
stuff_length <= std_logic_vector(to_unsigned(5, 3));
......@@ -2124,10 +2120,6 @@ begin
then
ack_err_i <= '1';
end if;
if (rx_data_nbs = DOMINANT) then
ack_received <= '1';
end if;
-------------------------------------------------------------------
-- Secondary ACK field (in FD Frames),or ACK Delimiter if RECESSIVE
......@@ -2148,10 +2140,6 @@ begin
crc_err_i <= '1';
end if;
if (rx_data_nbs = DOMINANT) then
ack_received <= '1';
end if;
-------------------------------------------------------------------
-- ACK Delimiter
-------------------------------------------------------------------
......
......@@ -1882,9 +1882,6 @@ package can_components is
-- Transmitted frame is valid
tran_valid :out std_logic;
-- ACK received
ack_received :out std_logic;
-- CRC calculation enabled
crc_enable :out std_logic;
......@@ -2245,9 +2242,6 @@ package can_components is
-----------------------------------------------------------------------
-- Status signals
-----------------------------------------------------------------------
-- ACK received
ack_received :out std_logic;
-- Bit rate shifted
br_shifted :out std_logic;
......
......@@ -371,8 +371,6 @@ package drv_stat_pkg is
constant STAT_EWL_REACHED_INDEX : natural := 253;
constant STAT_ERR_VALID_INDEX : natural := 254;
constant STAT_ACK_RECIEVED_OUT_INDEX : natural := 255;
constant STAT_BIT_ERR_VALID_INDEX : natural := 256;
constant STAT_BS_CTR_HIGH : natural := 302;
......
......@@ -259,7 +259,6 @@ architecture Protocol_Control_unit_test of CAN_test is
signal rec_valid_1 : std_logic;
-- Status signals
signal ack_received_1 : std_logic;
signal br_shifted_1 : std_logic;
signal form_err_1 : std_logic;
signal ack_err_1 : std_logic;
......@@ -368,7 +367,6 @@ architecture Protocol_Control_unit_test of CAN_test is
signal rec_valid_2 : std_logic;
-- Status signals
signal ack_received_2 : std_logic;
signal br_shifted_2 : std_logic;
signal form_err_2 : std_logic;
signal ack_err_2 : std_logic;
......@@ -769,7 +767,6 @@ begin
rec_valid => rec_valid_1,
-- Status signals
ack_received => ack_received_1,
br_shifted => br_shifted_1,
form_err => form_err_1,
ack_err => ack_err_1,
......@@ -890,7 +887,6 @@ begin
rec_valid => rec_valid_2,
-- Status signals
ack_received => ack_received_2,
br_shifted => br_shifted_2,
form_err => form_err_2,
ack_err => ack_err_2,
......
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