Commit 10e81648 authored by Ille, Ondrej, Ing.'s avatar Ille, Ondrej, Ing.
Browse files

Merge branch '132-interrupt-enable-mask-status' into 'master'

Resolve "interrupt enable/mask/status"

Closes #132

See merge request illeondr/CAN_FD_IP_Core!72
parents 38a9df35 48c7c3ab
......@@ -4760,7 +4760,7 @@ Address: 0x8
Size: 2 bytes
\end_layout
\begin_layout Standard
Reading this register returns Interrupt vector (status of generated Interrupts). Writing logic 1 to any bit clears according interrupt. Writing logic 0 has no effect.
Reading this register returns logic 1 for each interrupt which was captured (interrupt vector). Writing logic 1 to any bit clears according bit of captured interrupt. Writing logic 0 has no effect.
\end_layout
\begin_layout Standard
\noindent
......@@ -5308,7 +5308,7 @@ Address: 0xC
Size: 2 bytes
\end_layout
\begin_layout Standard
Writing logic 1 to a bit enables according interrupt.Writing logic 0 has no effect. Reading the register returns logic 1 in every bit whose interrupt capturing is enabled.
Writing logic 1 to a bit enables according interrupt. Writing logic 0 has no effect. Reading this register returns logic 1 for each enabled interrupt. If interrupt is captured in INT_STAT, enabled interrupt will cause "int" output to be asserted. Interrupts are level-based. To capture interrupt to INT_STAT register, interrupt must be unmasked.
\end_layout
\begin_layout Standard
\noindent
......@@ -5823,7 +5823,7 @@ Address: 0x10
Size: 2 bytes
\end_layout
\begin_layout Standard
Writing logic 1 disables according interrupt. Writing logic 0 has no effect. Reading this register has no effect.
Writing logic 1 disables according interrupt. Writing logic 0 has no effect. Reading this register has no effect. Disabled interrupt wil not affect "int" output of CAN Core event if it is captured in INT_STAT register.
\end_layout
\begin_layout Standard
\noindent
......@@ -6338,7 +6338,7 @@ Address: 0x14
Size: 2 bytes
\end_layout
\begin_layout Standard
Writing logic 1 masks according interrupt. Writing logic 0 has no effect. Reading this register returns status of the interrupt mask. Masked interrupt is captured, and can be read from INT_STAT, but does not affect interrupt output of the CAN Core.
Writing logic 1 masks according interrupt. Writing logic 0 has no effect. Reading this register returns logic 1 for each masked interrupt. If particular interrupt is masked, it won't be captured in INT_STAT register when internal conditions for this interrupt are met (e.g RX Buffer is not empty for RXNEI).
\end_layout
\begin_layout Standard
\noindent
......@@ -6853,7 +6853,7 @@ Address: 0x18
Size: 2 bytes
\end_layout
\begin_layout Standard
Writing logic 1 un-masks according interrupt. Writing logic 0 has no effect. Reading this register has no effect. Un-masked interrupt is captured, can be read from INT_STAT, and it does affect interrupt output of the CAN Core.
Writing logic 1 un-masks according interrupt. Writing logic 0 has no effect. Reading this register has no effect. If particular interrupt is un-masked, it will be captured in INT_STAT register when internal conditions for this interrupt are met (e.g RX Buffer is not empty for RXNEI).
\end_layout
\begin_layout Standard
\noindent
......
......@@ -534,7 +534,7 @@
<ipxact:register>
<ipxact:name>INT_STAT</ipxact:name>
<ipxact:displayName>INT_STAT</ipxact:displayName>
<ipxact:description>Reading this register returns Interrupt vector (status of generated Interrupts). Writing logic 1 to any bit clears according interrupt. Writing logic 0 has no effect.</ipxact:description>
<ipxact:description>Reading this register returns logic 1 for each interrupt which was captured (interrupt vector). Writing logic 1 to any bit clears according bit of captured interrupt. Writing logic 0 has no effect.</ipxact:description>
<ipxact:dim>0</ipxact:dim>
<ipxact:addressOffset>'h8</ipxact:addressOffset>
<ipxact:size>16</ipxact:size>
......@@ -724,7 +724,7 @@
<ipxact:register>
<ipxact:name>INT_ENA_CLR</ipxact:name>
<ipxact:displayName>INT_ENA_CLR</ipxact:displayName>
<ipxact:description>Writing logic 1 disables according interrupt. Writing logic 0 has no effect. Reading this register has no effect.</ipxact:description>
<ipxact:description>Writing logic 1 disables according interrupt. Writing logic 0 has no effect. Reading this register has no effect. Disabled interrupt wil not affect &quot;int&quot; output of CAN Core event if it is captured in INT_STAT register.</ipxact:description>
<ipxact:dim>0</ipxact:dim>
<ipxact:addressOffset>'h10</ipxact:addressOffset>
<ipxact:size>16</ipxact:size>
......@@ -746,7 +746,7 @@
<ipxact:register>
<ipxact:name>INT_MASK_CLR</ipxact:name>
<ipxact:displayName>INT_MASK_CLR</ipxact:displayName>
<ipxact:description>Writing logic 1 un-masks according interrupt. Writing logic 0 has no effect. Reading this register has no effect. Un-masked interrupt is captured, can be read from INT_STAT, and it does affect interrupt output of the CAN Core.</ipxact:description>
<ipxact:description>Writing logic 1 un-masks according interrupt. Writing logic 0 has no effect. Reading this register has no effect. If particular interrupt is un-masked, it will be captured in INT_STAT register when internal conditions for this interrupt are met (e.g RX Buffer is not empty for RXNEI).</ipxact:description>
<ipxact:dim>0</ipxact:dim>
<ipxact:addressOffset>'h18</ipxact:addressOffset>
<ipxact:size>16</ipxact:size>
......@@ -768,7 +768,7 @@
<ipxact:register>
<ipxact:name>INT_MASK_SET</ipxact:name>
<ipxact:displayName>INT_MASK_SET</ipxact:displayName>
<ipxact:description>Writing logic 1 masks according interrupt. Writing logic 0 has no effect. Reading this register returns status of the interrupt mask. Masked interrupt is captured, and can be read from INT_STAT, but does not affect interrupt output of the CAN Core.</ipxact:description>
<ipxact:description>Writing logic 1 masks according interrupt. Writing logic 0 has no effect. Reading this register returns logic 1 for each masked interrupt. If particular interrupt is masked, it won't be captured in INT_STAT register when internal conditions for this interrupt are met (e.g RX Buffer is not empty for RXNEI).</ipxact:description>
<ipxact:dim>0</ipxact:dim>
<ipxact:addressOffset>'h14</ipxact:addressOffset>
<ipxact:size>16</ipxact:size>
......@@ -790,7 +790,7 @@
<ipxact:register>
<ipxact:name>INT_ENA_SET</ipxact:name>
<ipxact:displayName>INT_ENA_SET</ipxact:displayName>
<ipxact:description>Writing logic 1 to a bit enables according interrupt.Writing logic 0 has no effect. Reading the register returns logic 1 in every bit whose interrupt capturing is enabled.</ipxact:description>
<ipxact:description>Writing logic 1 to a bit enables according interrupt. Writing logic 0 has no effect. Reading this register returns logic 1 for each enabled interrupt. If interrupt is captured in INT_STAT, enabled interrupt will cause &quot;int&quot; output to be asserted. Interrupts are level-based. To capture interrupt to INT_STAT register, interrupt must be unmasked.</ipxact:description>
<ipxact:dim>0</ipxact:dim>
<ipxact:addressOffset>'hC</ipxact:addressOffset>
<ipxact:size>16</ipxact:size>
......
......@@ -172,8 +172,8 @@ begin
int_mask <= int_mask_reg;
int_ena <= int_ena_reg;
int_out <= '1' when (int_vect_reg and int_mask_reg) /= zero_mask else
'0';
int_out <= '0' when (int_vect_reg and int_ena_reg) = zero_mask else
'1';
-- Interrupt register masking and enabling
int_input_active(BEI_IND) <= error_valid;
......@@ -221,7 +221,7 @@ begin
end if;
-- Interrupt status (vector)
if (int_input_active(i) = '1' and int_ena_reg(i) = '1') then
if (int_input_active(i) = '1' and int_mask_reg(i) = '0') then
int_vect_reg(i) <= '1';
elsif (drv_int_vect_clr(i) = '1') then
int_vect_reg(i) <= '0';
......
......@@ -317,9 +317,9 @@ package CAN_FD_register_map is
------------------------------------------------------------------------------
-- INT_STAT register
--
-- Reading this register returns Interrupt vector (status of generated Interru
-- pts). Writing logic 1 to any bit clears according interrupt. Writing logic
-- 0 has no effect.
-- Reading this register returns logic 1 for each interrupt which was captured
-- (interrupt vector). Writing logic 1 to any bit clears according bit of cap
-- tured interrupt. Writing logic 0 has no effect.
------------------------------------------------------------------------------
constant RI_IND : natural := 0;
constant TI_IND : natural := 1;
......@@ -351,9 +351,11 @@ package CAN_FD_register_map is
------------------------------------------------------------------------------
-- INT_ENA_SET register
--
-- Writing logic 1 to a bit enables according interrupt.Writing logic 0 has no
-- effect. Reading the register returns logic 1 in every bit whose interrupt
-- capturing is enabled.
-- Writing logic 1 to a bit enables according interrupt. Writing logic 0 has n
-- o effect. Reading this register returns logic 1 for each enabled interrupt.
-- If interrupt is captured in INT_STAT, enabled interrupt will cause "int" o
-- utput to be asserted. Interrupts are level-based. To capture interrupt to I
-- NT_STAT register, interrupt must be unmasked.
------------------------------------------------------------------------------
constant INT_ENA_SET_L : natural := 0;
constant INT_ENA_SET_H : natural := 11;
......@@ -365,7 +367,8 @@ package CAN_FD_register_map is
-- INT_ENA_CLR register
--
-- Writing logic 1 disables according interrupt. Writing logic 0 has no effect
-- . Reading this register has no effect.
-- . Reading this register has no effect. Disabled interrupt wil not affect "i
-- nt" output of CAN Core event if it is captured in INT_STAT register.
------------------------------------------------------------------------------
constant INT_ENA_CLR_L : natural := 0;
constant INT_ENA_CLR_H : natural := 11;
......@@ -377,9 +380,10 @@ package CAN_FD_register_map is
-- INT_MASK_SET register
--
-- Writing logic 1 masks according interrupt. Writing logic 0 has no effect. R
-- eading this register returns status of the interrupt mask. Masked interrupt
-- is captured, and can be read from INT_STAT, but does not affect interrupt
-- output of the CAN Core.
-- eading this register returns logic 1 for each masked interrupt. If particul
-- ar interrupt is masked, it won't be captured in INT_STAT register when inte
-- rnal conditions for this interrupt are met (e.g RX Buffer is not empty for
-- RXNEI).
------------------------------------------------------------------------------
constant INT_MASK_SET_L : natural := 0;
constant INT_MASK_SET_H : natural := 11;
......@@ -391,9 +395,9 @@ package CAN_FD_register_map is
-- INT_MASK_CLR register
--
-- Writing logic 1 un-masks according interrupt. Writing logic 0 has no effect
-- . Reading this register has no effect. Un-masked interrupt is captured, can
-- be read from INT_STAT, and it does affect interrupt output of the CAN Core
-- .
-- . Reading this register has no effect. If particular interrupt is un-masked
-- , it will be captured in INT_STAT register when internal conditions for thi
-- s interrupt are met (e.g RX Buffer is not empty for RXNEI).
------------------------------------------------------------------------------
constant INT_MASK_CLR_L : natural := 0;
constant INT_MASK_CLR_H : natural := 11;
......
......@@ -103,7 +103,7 @@ architecture int_man_unit_test of CAN_test is
signal loger_finished : std_logic := '0';
-- RX Buffer not empty
signal rx_empty : std_logic := '0';
signal rx_empty : std_logic := '1';
-- HW command on TX Buffer
signal txt_hw_cmd : txt_hw_cmd_type;
......@@ -449,7 +449,7 @@ begin
end if;
-- Interrupt clear and capturing!
if (int_input(i) = '1' and int_ena(i) = '1') then
if (int_input(i) = '1' and int_mask_exp(i) = '0') then
int_status_exp(i) <= '1';
elsif (drv_int_clear(i) = '1') then
int_status_exp(i) <= '0';
......@@ -457,7 +457,7 @@ begin
end loop;
-- Calculating expected interrupt output
if ((int_vector AND int_mask) = zeroes) then
if ((int_vector AND int_ena_exp) = zeroes) then
exp_output := false;
else
exp_output := true;
......
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