Commit 0eeb6784 authored by Ille, Ondrej, Ing.'s avatar Ille, Ondrej, Ing.

Added reset synchroniser

parent 004841f1
......@@ -1908,11 +1908,34 @@ clk_sys
\series default
.
Every other time period is derived from clk_sys (Time quantum, Bit time...).
Every register has
The main core reset
\begin_inset Quotes eld
\end_inset
res_n
\begin_inset Quotes erd
\end_inset
is an
\series bold
asynchronous reset
\series default
, res_n, which is active low, by default.
(active low) and it is internally synchronised by two flip-flop synchroniser
to avoid possible problems with reset recovery time.
After
\begin_inset Quotes eld
\end_inset
res_n
\begin_inset Quotes erd
\end_inset
is released
\series bold
at least two clock cycles
\series default
must elapse before the core is accessed, otherwise write to the Core will
have no effect and read will return zero values.
The design is intended to be latch-free.
\end_layout
This diff is collapsed.
......@@ -33,7 +33,7 @@ use work.CANcomponents.ALL;
-- 22.6.2016 1. Added rec_esi signal for error state propagation into the RX buffer.
-- 2. Added explicit architecture selection for each component (RTL)
-- 24.8.2016 Added "use_logger" generic to the registers module.
--
-- 28.11.2017 Added "rst_sync_comp" reset synchroniser.
-------------------------------------------------------------------------------------------------------------
-------------------------------------------------------------------------------------------------------------
......@@ -105,7 +105,8 @@ entity CAN_top_level is
---------------------
--Internal signals --
---------------------
signal res_n_int : std_logic;
signal res_n_int : std_logic; -- Overal reset (External+Reset by memory access)
signal res_n_sync : std_logic; -- Synchronised reset
signal drv_bus : std_logic_vector(1023 downto 0);
signal stat_bus : std_logic_vector(511 downto 0);
......@@ -237,10 +238,18 @@ architecture rtl of CAN_top_level is
for core_top_comp : core_top use entity work.core_top(rtl);
for prescaler_comp : prescaler_v3 use entity work.prescaler_v3(rtl);
for bus_sync_comp : busSync use entity work.busSync(rtl);
for rst_sync_comp : rst_sync use entity work.rst_sync(rtl);
--for log_comp : CAN_logger use entity work.CAN_logger(rtl);
begin
rst_sync_comp:rst_sync
port map(
clk => clk_sys,
arst_n => res_n,
rst_n => res_n_sync
);
reg_comp:registers
generic map(
compType => CAN_COMPONENT_TYPE,
......@@ -249,7 +258,7 @@ begin
)
port map(
clk_sys => clk_sys,
res_n => res_n,
res_n => res_n_sync,
res_out => res_n_int,
data_in => data_in,
data_out => data_out,
......
......@@ -29,6 +29,7 @@ USE WORK.CANconstants.ALL;
-- Revision History:
--
-- 15.11.2017 Created file
-- 27.11.2017 Added "rst_sync" asynchronous rest synchroniser circuit
-------------------------------------------------------------------------------------------------------------
---------------------------------------------------------------------------------------------------------------
......@@ -765,6 +766,17 @@ end component;
);
end component;
---------------------------------------
--Asynchronous resset synchroniser --
---------------------------------------
component rst_sync is
port (
signal clk : in std_logic;
signal arst_n : in std_logic;
signal rst_n : out std_logic
);
end component;
end package;
Library ieee;
use ieee.std_logic_1164.all;
-------------------------------------------------------------------------------------------------------------
--
-- CAN with Flexible Data-Rate IP Core
--
-- Copyright (C) 2015 Ondrej Ille <ondrej.ille@gmail.com>
--
-- This program is free software; you can redistribute it and/or
-- modify it under the terms of the GNU General Public License
-- as published by the Free Software Foundation; either version 2
-- of the License, or (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- The CAN protocol is developed by Robert Bosch GmbH and
-- protected by patents. Anybody who wants to implement this
-- IP core on silicon has to obtain a CAN protocol license
-- from Bosch.
--
--
-- Revision History:
--
-- 27.11.2017 Created file
--
-------------------------------------------------------------------------------------------------------------
-------------------------------------------------------------------------------------------------------------
-- Purpose:
-- Asynchronouse reset synchroniser to avoid problems with Reset recovery time.
-------------------------------------------------------------------------------------------------------------
entity rst_sync is
port (
signal clk : in std_logic;
signal arst_n : in std_logic;
signal rst_n : out std_logic
);
end rst_sync;
architecture rtl of rst_sync is
signal rff : std_logic;
begin
process (clk, arst_n)
begin
if (arst_n = '0') then
rff <= '0';
rst_n <= '0';
elsif (rising_edge(clk)) then
rff <= '1';
rst_n <= rff;
end if;
end process;
end rtl;
......@@ -33,6 +33,9 @@ use work.CANconstants.all;
-- 27.5.2016 Created file
-- 13.1.2017 Added formatting of identifier in CAN_send_frame, CAN_read_frame to fit the native
-- decimal interpretation (the same way as in C driver)
-- 27.11.2017 Added "reset_test" function fix. Implemented reset synchroniser to avoid async reset in
-- the core. As consequnce after the core reset is released, the core has to wait at least TWO clock
-- cycles till the reset is synchronised and deasserted.
-------------------------------------------------------------------------------------------------------------
......@@ -537,6 +540,7 @@ procedure reset_test
res_n <= '1';
status <= running;
error_ctr <= 0;
wait for 250 ns;
end procedure;
---------------------------------------------------------------------------------------
......
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