Commit 0d9e03d9 authored by Ille, Ondrej, Ing.'s avatar Ille, Ondrej, Ing.

Merge branch 'resource_optimizations' into 'master'

Resource optimizations

See merge request illeondr/CAN_FD_IP_Core!5
parents ca9fe089 7d0f4160
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This diff is collapsed.
This diff is collapsed.
......@@ -48,7 +48,14 @@ use work.ID_transfer.all;
------------------------------------------------------------------------------------------------------------
entity messageFilter is
PORT(
generic
(
constant sup_filtA :boolean := true; --Optional synthesis of received message filters
constant sup_filtB :boolean := true; -- By default the behaviour is as if all the filters are present
constant sup_filtC :boolean := true;
constant sup_range :boolean := true
);
port(
----------
--INPUTS--
----------
......@@ -142,30 +149,45 @@ begin
"0000" when others;
--Filter A input frame type filtering
int_filter_A_valid <= '1' when ( ( --Identifier matches the bits and mask
(rec_ident_in AND drv_filter_A_mask) =
(drv_filter_A_bits AND drv_filter_A_mask)
)
AND
( --Frame type Matches defined frame type
not((drv_filter_A_ctrl AND int_data_type)="0000")
)
)
else '0';
gen_filtA_pos: if (sup_filtA=true) generate
int_filter_A_valid <= '1' when ( ( --Identifier matches the bits and mask
(rec_ident_in AND drv_filter_A_mask) =
(drv_filter_A_bits AND drv_filter_A_mask)
)
AND
( --Frame type Matches defined frame type
not((drv_filter_A_ctrl AND int_data_type)="0000")
)
)
else '0';
end generate;
gen_filtA_neg: if (sup_filtA=false) generate
int_filter_A_valid <= '0';
end generate;
--Filter B input frame type filtering
int_filter_B_valid <= '1' when ( ( --Identifier matches the bits and mask
(rec_ident_in AND drv_filter_B_mask) =
(drv_filter_B_bits AND drv_filter_B_mask)
)
AND
( --Frame type Matches defined frame type
not((drv_filter_B_ctrl AND int_data_type)="0000")
gen_filtB_pos: if (sup_filtB=true) generate
int_filter_B_valid <= '1' when ( ( --Identifier matches the bits and mask
(rec_ident_in AND drv_filter_B_mask) =
(drv_filter_B_bits AND drv_filter_B_mask)
)
AND
( --Frame type Matches defined frame type
not((drv_filter_B_ctrl AND int_data_type)="0000")
)
)
)
else '0';
else '0';
end generate;
gen_filtB_neg: if (sup_filtB=false) generate
int_filter_B_valid <= '0';
end generate;
--Filter C input frame type filtering
gen_filtC_pos: if (sup_filtC=true) generate
int_filter_C_valid <= '1' when ( ( --Identifier matches the bits and mask
(rec_ident_in AND drv_filter_C_mask) =
(drv_filter_C_bits AND drv_filter_C_mask)
......@@ -176,19 +198,30 @@ begin
)
)
else '0';
end generate;
gen_filtC_neg: if (sup_filtC=false) generate
int_filter_C_valid <= '0';
end generate;
--Range filter for identifiers
ID_reg_to_decimal(rec_ident_in,rec_ident_dec);
int_filter_ran_valid <= '1' when ( --Identifier matches the range set
( rec_ident_dec<=to_integer(unsigned(drv_filter_ran_hi_th)) )
AND
( rec_ident_dec>=to_integer(unsigned(drv_filter_ran_lo_th)) )
)
AND
( --Frame type Matches defined frame type
not((drv_filter_ran_ctrl AND int_data_type)="0000")
)
else '0';
gen_filtRan_pos: if (sup_range=true) generate
ID_reg_to_decimal(rec_ident_in,rec_ident_dec);
int_filter_ran_valid <= '1' when ( --Identifier matches the range set
( rec_ident_dec<=to_integer(unsigned(drv_filter_ran_hi_th)) )
AND
( rec_ident_dec>=to_integer(unsigned(drv_filter_ran_lo_th)) )
)
AND
( --Frame type Matches defined frame type
not((drv_filter_ran_ctrl AND int_data_type)="0000")
)
else '0';
end generate;
gen_filtRan_neg: if (sup_range=false) generate
int_filter_ran_valid <= '0';
end generate;
--If received message is valid and at least one of
......@@ -204,7 +237,6 @@ begin
else rec_ident_valid;
---------------------------------------------------
--To avoid long combinational paths, valid filter
-- output is pipelined. This is OK since received
......
......@@ -37,6 +37,10 @@ use work.ID_transfer.all;
-- in unit test simulator was throwing out milions of warnings!
-- 23.6.2016 Added less or equal to the case when both timestamps and both identifiers are equal.
-- Thisway identifier from Buffer 1 instead of Buffer 2 is propagated!
-- 4.12.2017 Added support for split "Data" and "Metadata" into TXT Buffer. Added state machine
-- "tx_arb_fsm". The state machine waits for CAN Core to finish the transmission before
-- signalling the TXT Buffer to erase. Output data word is selected based on stored
-- value of "mess_src" from the time of decision between TXT1 and TXT2 buffer.
--
-------------------------------------------------------------------------------------------------------------------------------------------------------
......@@ -47,23 +51,30 @@ use work.ID_transfer.all;
-- for CAN Core when the time Stamp of message is higher than actual timestamp! This realises the func-
-- tionality of sending the message in exact time! When both timeStamp are equal and then message with
-- lower identifier is selected!
--
-- Both input buffers may be set to "not allowed" by driving bus.
--
-----------------------------------------------------------------------------------------------------------
entity txArbitrator is
port(
------------------------
-- Clock and reset
------------------------
signal clk_sys :in std_logic;
signal res_n :in std_logic;
------------------------
--TX Buffers interface--
------------------------
--TXT Buffer 1
signal txt1_buffer_in :in std_logic_vector(639 downto 0); --Time TX1 buffer input
signal txt1buf_info_in :in std_logic_vector(639 downto 512); --Time TX1 buffer input
signal txt1buf_data_in :in std_logic_vector(31 downto 0); --Time TX1 buffer input
signal txt1_buffer_empty :in std_logic; --No message in Time TX Buffer
signal txt1_buffer_ack :out std_logic; --Time buffer acknowledge that
-- message can be erased
--TXT Buffer 2
signal txt2_buffer_in :in std_logic_vector(639 downto 0); --Time TX1 buffer input
signal txt2buf_info_in :in std_logic_vector(639 downto 512); --Time TX2 buffer input
signal txt2buf_data_in :in std_logic_vector(31 downto 0); --Time TX2 buffer input
signal txt2_buffer_empty :in std_logic; --No message in Time TX Buffer
signal txt2_buffer_ack :out std_logic; --Time buffer acknowledge that
-- message can be erased
......@@ -71,7 +82,7 @@ entity txArbitrator is
-----------------------
--CAN Core Interface---
-----------------------
signal tran_data_out :out std_logic_vector(511 downto 0); --TX Message data
signal tran_data_word_out :out std_logic_vector(31 downto 0); --TX Message data
signal tran_ident_out :out std_logic_vector(28 downto 0); --TX Identifier
signal tran_dlc_out :out std_logic_vector(3 downto 0); --TX Data length code
signal tran_is_rtr :out std_logic; --TX is remote frame
......@@ -80,9 +91,14 @@ entity txArbitrator is
signal tran_brs_out :out std_logic; --Bit rate shift for CAN FD frames
signal tran_frame_valid_out :out std_logic; --Signal for CAN Core that frame on the
-- output is valid and can be stored for transmitting
-- Acknowledge from CAN core that frame transmission started and
-- that frame informations were stored
signal tran_data_ack :in std_logic;
-- Acknowledge that CAN core that frame was succesfully transmitted
-- and can be erased.
signal tran_valid :in std_logic;
signal tran_data_ack :in std_logic; --Acknowledge from CAN core that acutal message was
-- stored into internal buffer for transmitting
---------------------
--Driving interface--
---------------------
......@@ -96,6 +112,7 @@ entity txArbitrator is
--------------------
signal valid_join :std_logic_vector(1 downto 0); --Joined signal for valid signals from buffers
signal mess_src :std_logic; --Message source (0-normal buffer, 1-Time based buffer)
signal mess_src_reg :std_logic; -- Message source of the actually transmitted frame
-------------------
--Internal aliases-
......@@ -136,6 +153,8 @@ entity txArbitrator is
signal mt1_lt_ts :boolean;
signal mt2_lt_ts :boolean;
--State machine for following when the frame was already transmitted!
signal tx_arb_fsm :tx_arb_state_type;
end entity;
......@@ -151,12 +170,12 @@ begin
((not txt2_buffer_empty) and (drv_allow_txt2));
--Transmit time of TXT Buffer messages (from both buffers)
mess_time1 <= txt1_buffer_in(TXT_TSUPP_HIGH downto TXT_TSLOW_LOW);
mess_time2 <= txt2_buffer_in(TXT_TSUPP_HIGH downto TXT_TSLOW_LOW);
mess_time1 <= txt1buf_info_in(TXT_TSUPP_HIGH downto TXT_TSLOW_LOW);
mess_time2 <= txt2buf_info_in(TXT_TSUPP_HIGH downto TXT_TSLOW_LOW);
--Transmit identifiers
ident1 <= txt1_buffer_in(TXT_IDW_HIGH-3 downto TXT_IDW_LOW);
ident2 <= txt2_buffer_in(TXT_IDW_HIGH-3 downto TXT_IDW_LOW);
ident1 <= txt1buf_info_in(TXT_IDW_HIGH-3 downto TXT_IDW_LOW);
ident2 <= txt2buf_info_in(TXT_IDW_HIGH-3 downto TXT_IDW_LOW);
--Comparator methods for 64 bit vectors
mt1_lt_mt2 <= less_than(mess_time1,mess_time2);
......@@ -235,7 +254,7 @@ begin
----------------------------------------------------------------------
----------------------------------------------------------------------
----Multiplexing data from buffers into message lines to CAN Core ----
---- Multiplexing data from buffers into message lines to CAN Core ---
----------------------------------------------------------------------
----------------------------------------------------------------------
......@@ -243,23 +262,23 @@ begin
--Frame format word--
---------------------
--Data length Code
tran_dlc_out <= txt1_buffer_in(611 downto 608) when mess_src='0' else
txt2_buffer_in(611 downto 608);
tran_dlc_out <= txt1buf_info_in(611 downto 608) when mess_src='0' else
txt2buf_info_in(611 downto 608);
--RTR Frame
tran_is_rtr <= txt1_buffer_in(613) when mess_src='0' else
txt2_buffer_in(613);
tran_is_rtr <= txt1buf_info_in(613) when mess_src='0' else
txt2buf_info_in(613);
--Identifier Type
tran_ident_type_out <= txt1_buffer_in(614) when mess_src='0' else
txt2_buffer_in(614);
tran_ident_type_out <= txt1buf_info_in(614) when mess_src='0' else
txt2buf_info_in(614);
--Frame Type
tran_frame_type_out <= txt1_buffer_in(615) when mess_src='0' else
txt2_buffer_in(615);
tran_frame_type_out <= txt1buf_info_in(615) when mess_src='0' else
txt2buf_info_in(615);
--Bit rate shift
tran_brs_out <= txt1_buffer_in(617) when mess_src='0' else
txt2_buffer_in(617);
tran_brs_out <= txt1buf_info_in(617) when mess_src='0' else
txt2buf_info_in(617);
-----------------------------------------------------------------------
--NOTE: TimeStamp Words skipped since timeStamp prioritization is
--NOTE: TimeStamp Words skipped since Timestamp prioritization is
-- already achieved by comparing actual and message timestamps
-- inside TxArbitrator.
-----------------------------------------------------------------------
......@@ -267,18 +286,70 @@ begin
----------------------------------
--Identifier word and data words--
----------------------------------
tran_ident_out <= txt1_buffer_in(540 downto 512) when mess_src='0' else
txt2_buffer_in(540 downto 512);
tran_data_out <= txt1_buffer_in(511 downto 0) when mess_src='0' else
txt2_buffer_in(511 downto 0);
tran_ident_out <= txt1buf_info_in(540 downto 512) when mess_src='0' else
txt2buf_info_in(540 downto 512);
-------------------------------------------------------------
--Confirmation for TX or TXT Buffer that message was stored--
-- the in CAN Core and it can be erased from TXT buffer --
-------------------------------------------------------------
txt1_buffer_ack <= '1' when ((tran_data_ack='1') AND (mess_src='0')) else
'0';
txt2_buffer_ack <= '1' when ((tran_data_ack='1') AND (mess_src='1')) else
'0';
--Data which goes to the CAN Core has to be decided on message source
-- which was sampled when frame info was stored into Core. This way even if
-- the other buffer is modified, the data source remain correct for the whole
-- duration of transmission!
tran_data_word_out <= txt1buf_data_in when mess_src_reg='0' else
txt2buf_data_in when mess_src_reg='1' else
(OTHERS => '0');
--------------------------------------------------------------------------------
-- State machine for deciding whether the frame transmission finished and
-- it can be already erased.
--------------------------------------------------------------------------------
proc_txarb_fsm:process(clk_sys,res_n)
begin
if (res_n=ACT_RESET) then
tx_arb_fsm <= arb_idle;
mess_src_reg <= '0';
elsif rising_edge(clk_sys) then
tx_arb_fsm <= tx_arb_fsm;
mess_src_reg <= mess_src_reg;
--By default we dont give acknowledge to any buffer
txt1_buffer_ack <= '0';
txt2_buffer_ack <= '0';
case tx_arb_fsm is
--------------------------------------------------------------------------------
-- Waiting for Protocol control to give command that it stored the 4 words with
-- information and start the transmission...
--------------------------------------------------------------------------------
when arb_idle =>
if (tran_data_ack='1') then
tx_arb_fsm <= arb_trans;
mess_src_reg <= mess_src; -- Store when frame info is loaded to the Core
end if;
--------------------------------------------------------------------------------
-- Waiting for signal that frame transmission ended succesfully and buffer can
-- be erased!
--------------------------------------------------------------------------------
when arb_trans =>
if (tran_valid = '1')then
tx_arb_fsm <= arb_idle;
if (mess_src_reg = '0') then
txt1_buffer_ack <= '1';
elsif (mess_src_reg = '1') then
txt2_buffer_ack <= '1';
else
txt1_buffer_ack <= '0';
txt2_buffer_ack <= '0';
end if;
end if;
when others =>
report "Error - Unknow TX Arbitrator state" severity error;
end case;
end if;
end process;
end architecture;
\ No newline at end of file
......@@ -31,6 +31,11 @@ use work.CANconstants.all;
-- July 2015 Created file
-- 30.11.2017 Changed the buffer implementation from parallel into 32*20 buffer of data. Reading so far
-- left parallel. User is directly accessing the buffer and storing the data to it.
-- 04.12.2017 Buffer split to "Frame metadata" (txt_buffer_info) and "Data" (txt_buffer_data). Frame
-- metadata consists of first 4 words (Frame format, Timestamps and Identifier). Frame metadata
-- are available combinationally at all times. Frame data are accessed directly from CAN Core
-- by new pointer "txt_data_addr". txt_buffer_data is synthesized as RAM memory and significant
-- reource reduction was achieved.
-------------------------------------------------------------------------------------------------------------------------------------------------------
-----------------------------------------------------------------------------------------------------------
......@@ -68,8 +73,17 @@ entity txtBuffer is
------------------------------------
--CAN Core and TX Arbiter Interface-
------------------------------------
signal txt_buffer_out :out std_logic_vector(639 downto 0); --Output value of message in the buffer
signal txt_data_ack :in std_logic --Signal from TX Arbiter that data were sent and buffer can be erased
--Signal from TX Arbiter that data were transmitted and buffer can be erased
signal txt_data_ack :in std_logic;
-- Frame to be transmitted
signal txt_data_word :out std_logic_vector(31 downto 0);
signal txt_data_addr :in natural range 0 to 15;
--First 4 words (frame format, timestamps, identifier) are available combinationally,
--to be able instantly decide on higher priority frame
signal txt_frame_info_out :out std_logic_vector(127 downto 0)
);
end entity;
......@@ -80,13 +94,17 @@ architecture rtl of txtBuffer is
----------------------
--Internal registers--
----------------------
type memory is array(0 to 19) of
type frame_data_memory is array(0 to 15) of
std_logic_vector(31 downto 0);
type frame_info_memory is array (0 to 3) of
std_logic_vector(31 downto 0);
------------------
--Signal aliases--
------------------
signal txt_buffer : memory; -- Time transcieve buffer
signal txt_buffer_data : frame_data_memory; -- Time transcieve buffer - Data memory
signal txt_buffer_info : frame_info_memory; -- Frame format, Timestamps and Identifier
signal tran_wr : std_logic_vector(1 downto 0); -- Store into TXT buffer 1 or 2
signal txt_empty_reg : std_logic; -- Status of the register
......@@ -104,24 +122,12 @@ begin
drv_bus(DRV_ALLOW_TXT2_INDEX) when ID=2 else
'0';
--Output assignment and aliases
-- So far reading of the data from buffer is parelell. It will be modified to reading by word...
sizegen_fd: if (useFDsize=true) generate
txt_buffer_out <= txt_buffer(0)&txt_buffer(1)&txt_buffer(2)&txt_buffer(3)&
txt_buffer(4)&txt_buffer(5)&txt_buffer(6)&txt_buffer(7)&txt_buffer(8)&
txt_buffer(9)&txt_buffer(10)&txt_buffer(11)&txt_buffer(12)&txt_buffer(13)&
txt_buffer(14)&txt_buffer(15)&txt_buffer(16)&txt_buffer(17)&txt_buffer(18)&txt_buffer(19);
end generate;
--Output data are given by the address from the Core
txt_data_word <= txt_buffer_data(txt_data_addr);
--First 4 words of the Frame are available constantly...
txt_frame_info_out <= txt_buffer_info(0)&txt_buffer_info(1)&txt_buffer_info(2)&txt_buffer_info(3);
--Since RAM is read only by TX Arbitrator and CAN Core, we can just disconnect the outputs
-- if we dont want to synthesize the Full FD support. Synthesizer will then remove part of the
-- memory/registers since there will be no fan-out.
sizegen_nofd: if (useFDsize=false) generate
txt_buffer_out(639 downto 448) <= txt_buffer(0)&txt_buffer(1)&txt_buffer(2)&txt_buffer(3)&
txt_buffer(4)&txt_buffer(5);
txt_buffer_out(446 downto 0) <= (OTHERS => '0');
end generate;
--------------------------------------------------------------------------------
-- Main buffer comment
--------------------------------------------------------------------------------
......@@ -129,11 +135,13 @@ begin
begin
if (res_n = ACT_RESET) then
-- In order to use RAM for the buffer, async reset cannot be done!
-- synthesis translate_off
txt_buffer <= (OTHERS => (OTHERS => '0'));
-- synthesis translate_on
-- In order to use RAM for the buffer, async reset cannot be done!
-- synthesis translate_off
txt_buffer_data <= (OTHERS => (OTHERS => '0'));
-- synthesis translate_on
-- Frame info is stored in registers
txt_buffer_info <= (OTHERS => (OTHERS => '0'));
txt_empty_reg <= '1';
elsif (rising_edge(clk_sys))then
......@@ -151,7 +159,11 @@ begin
--Store the data into the Buffer during the access
if (tran_wr(ID-1)='1') then
txt_buffer(to_integer(unsigned(tran_addr))) <= tran_data;
if (tran_addr<4) then
txt_buffer_info(to_integer(unsigned(tran_addr))) <= tran_data;
else
txt_buffer_data(to_integer(unsigned(tran_addr-4))) <= tran_data;
end if;
end if;
end if;
......
......@@ -77,7 +77,7 @@ entity core_top is
---------------------------
--Tx Arbitrator interface--
---------------------------
signal tran_data_in :in std_logic_vector(511 downto 0);
signal tran_data_in :in std_logic_vector(31 downto 0);
signal tran_ident_in :in std_logic_vector(28 downto 0);
signal tran_dlc_in :in std_logic_vector(3 downto 0);
signal tran_is_rtr_in :in std_logic;
......@@ -86,7 +86,8 @@ entity core_top is
signal tran_brs_in :in std_logic; --Frame should be transcieved with BRS value
signal tran_frame_valid_in :in std_logic; --Signal for CAN Core that frame on the output is valid and can be stored for transmitting
signal tran_data_ack_out :out std_logic; --Acknowledge from CAN core that acutal message was stored into internal buffer for transmitting
signal txt_buf_ptr :out natural range 0 to 15; --Pointer to TXT buffer memory
-----------------------------------------------
--Recieve Buffer and Message Filter Interface--
-----------------------------------------------
......@@ -225,7 +226,6 @@ entity core_top is
signal alc : std_logic_vector(4 downto 0);
--Transcieve buffer output
signal tran_data : std_logic_vector(511 downto 0);
signal tran_ident : std_logic_vector(28 downto 0);
signal tran_dlc : std_logic_vector(3 downto 0);
signal tran_is_rtr : std_logic;
......@@ -362,7 +362,6 @@ begin
port map(
clk_sys => clk_sys,
res_n => res_n,
tran_data_in => tran_data_in,
tran_ident_in => tran_ident_in,
tran_dlc_in => tran_dlc_in,
tran_is_rtr_in => tran_is_rtr_in,
......@@ -371,7 +370,6 @@ begin
tran_brs_in => tran_brs_in,
frame_store => frame_Store,
tran_data => tran_data,
tran_ident => tran_ident,
tran_dlc => tran_dlc,
tran_is_rtr => tran_is_rtr,
......@@ -407,7 +405,7 @@ begin
PC_State_out => PC_State,
alc => alc,
tran_data => tran_data,
tran_data => tran_data_in,
tran_ident => tran_ident,
tran_dlc => tran_dlc,
tran_is_rtr => tran_is_rtr,
......@@ -415,6 +413,7 @@ begin
tran_frame_type => tran_frame_type,
tran_brs => tran_brs,
br_shifted => br_shifted_int,
txt_buf_ptr => txt_buf_ptr,
hard_sync_edge => hard_sync_edge,
......
......@@ -97,6 +97,8 @@ use work.CANconstants.all;
-- and the memory was stored in LUT combinational memory! An additional effect of this change
-- is that Received Data are not erased in the SOF of next frame and thus it stays on the output
-- of CAN Core until it is rewritten by next data.
-- 4.12.2017 Added support for addressing of transmitted data directly from TXT buffer with "txt_buf_ptr",
-- instead of fetching data from "Tran Buffer" in CAN Core.
--
-------------------------------------------------------------------------------------------------------------
......@@ -120,7 +122,7 @@ entity protocolControl is
-------------------------------
--Transcieve buffer interface--
-------------------------------
signal tran_data :in std_logic_vector(511 downto 0);
signal tran_data :in std_logic_vector(31 downto 0);
signal tran_ident :in std_logic_vector(28 downto 0);
signal tran_dlc :in std_logic_vector(3 downto 0);
signal tran_is_rtr :in std_logic;
......@@ -131,6 +133,7 @@ entity protocolControl is
signal frame_store :out std_logic; --Store frame from TX Arbitrator to the Transcieve Buffer
signal tran_frame_valid_in :in std_logic; --Valid frame ready to be stored into Transcieeve Buffer
signal tran_data_ack :out std_logic; --Acknowledge that the frame was stored
signal txt_buf_ptr :out natural range 0 to 15; --Pointer to TXT buffer memory
-------------------------
--Recieved data output --
......@@ -369,6 +372,8 @@ entity protocolControl is
signal rec_dram_bind : natural range 0 to 3; --Byte index into RAM
signal rec_dram : rec_data_RAM_type;
signal txt_buf_ptr_r : natural range 0 to 15; --Pointer directly to TXT buffer to get the data
-----------------------
--CRC field registers--
-----------------------
......@@ -478,6 +483,8 @@ begin
rec_esi <= rec_esi_r;
ack_recieved_out <= ack_recieved;
--Pointer into TXT Buffer
txt_buf_ptr <= txt_buf_ptr_r;
-----------------------
--Auxiliarly vectors
......@@ -598,6 +605,9 @@ begin
rec_dram_bind <= 0;
rec_data_sr <= (OTHERS => '0');
-- Pointer directly to TXT Buffer RAM
txt_buf_ptr_r <= 0;
--Presetting the sampling point control
sp_control_r <= NOMINAL_SAMPLE;
ssp_reset_r <= '0';
......@@ -619,7 +629,7 @@ begin
rx_parity <= '0';
rx_count_grey <= (OTHERS =>'0');
elsif rising_edge(clk_sys)then
-----------------------------------------------------
......@@ -717,6 +727,8 @@ begin
rec_data_sr <= rec_data_sr;
rec_dram_ptr <= rec_dram_ptr;
rec_dram_bind <= rec_dram_bind;
txt_buf_ptr_r <= txt_buf_ptr_r;
if(drv_ena='0')then
PC_State <= off;
......@@ -1299,11 +1311,23 @@ begin
rec_dram_ptr <= 0;
rec_dram_bind <= 0;
rec_data_sr <= (OTHERS => '0');