Commit 0bc02f86 authored by Ille, Ondrej, Ing.'s avatar Ille, Ondrej, Ing.

Added Error counter reset command to register map.

parent 5bbde199
......@@ -4021,11 +4021,11 @@ Reserved\end_layout
\end_inset
</cell>
<cell alignment="center" leftline="true" multicolumn="2" topline="true" usebox="none" valignment="top">
<cell alignment="center" leftline="true" multicolumn="1" topline="true" usebox="none" valignment="top">
\begin_inset Text
\begin_layout Plain Layout
Reserved\end_layout
ERCRST\end_layout
\end_inset
</cell>
......@@ -4099,7 +4099,7 @@ Reset value\end_layout
\begin_inset Text
\begin_layout Plain Layout
-\end_layout
0\end_layout
\end_inset
</cell>
......@@ -4151,6 +4151,9 @@ RRB Release Receive buffer. This command deletes all data from the Receive buffe
\begin_layout Description
CDO Clear data overrun flag. This command will clear data overrun flag on RX Buffer.
\end_layout
\begin_layout Description
ERCRST Error counter reset. Issuing this command will erase TX, RX error counters after 128 conecutive ocurrences of 11 recessive bits. This command can be used as protocol compliant transition from Bus-off to Error Active. Upon completion, TX RX Error counters are erased and fault confinement state is set to Error Active.
\end_layout
\begin_layout Standard
\begin_inset VSpace bigskip
\end_inset
......
......@@ -143,7 +143,8 @@ union ctu_can_fd_mode_command_status_settings {
uint32_t at : 1;
uint32_t rrb : 1;
uint32_t cdo : 1;
uint32_t reserved_15_12 : 4;
uint32_t ercrst : 1;
uint32_t reserved_15_13 : 3;
/* STATUS */
uint32_t rbs : 1;
uint32_t dos : 1;
......@@ -173,7 +174,8 @@ union ctu_can_fd_mode_command_status_settings {
uint32_t tbs : 1;
uint32_t dos : 1;
uint32_t rbs : 1;
uint32_t reserved_15_12 : 4;
uint32_t reserved_15_13 : 3;
uint32_t ercrst : 1;
uint32_t cdo : 1;
uint32_t rrb : 1;
uint32_t at : 1;
......
......@@ -298,6 +298,18 @@
</ipxact:resets>
<ipxact:bitWidth>1</ipxact:bitWidth>
</ipxact:field>
<ipxact:field>
<ipxact:name>ERCRST</ipxact:name>
<ipxact:displayName>ERCRST</ipxact:displayName>
<ipxact:description>Error counter reset. Issuing this command will erase TX, RX error counters after 128 conecutive ocurrences of 11 recessive bits. This command can be used as protocol compliant transition from Bus-off to Error Active. Upon completion, TX RX Error counters are erased and fault confinement state is set to Error Active.</ipxact:description>
<ipxact:bitOffset>4</ipxact:bitOffset>
<ipxact:resets>
<ipxact:reset>
<ipxact:value>0</ipxact:value>
</ipxact:reset>
</ipxact:resets>
<ipxact:bitWidth>1</ipxact:bitWidth>
</ipxact:field>
</ipxact:register>
<ipxact:register>
<ipxact:name>STATUS</ipxact:name>
......
......@@ -247,11 +247,13 @@ package CAN_FD_register_map is
constant AT_IND : natural := 9;
constant RRB_IND : natural := 10;
constant CDO_IND : natural := 11;
constant ERCRST_IND : natural := 12;
-- COMMAND register reset values
constant AT_RSTVAL : std_logic := '0';
constant RRB_RSTVAL : std_logic := '0';
constant CDO_RSTVAL : std_logic := '0';
constant ERCRST_RSTVAL : std_logic := '0';
------------------------------------------------------------------------------
-- STATUS register
......
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