Commit 0ba13886 authored by Ille, Ondrej, Ing.'s avatar Ille, Ondrej, Ing.

src,test: Fix No positive resynchronisation.

Positive resynchronisation shall occur also when unit is receiver!
parent e4421ac8
Pipeline #19778 failed with stages
in 129 minutes and 57 seconds
......@@ -577,7 +577,6 @@ begin
nbt_ctrs_en => nbt_ctrs_en, -- OUT
dbt_ctrs_en => dbt_ctrs_en, -- OUT
sync_control => sync_control_i, -- OUT
no_pos_resync => no_pos_resync, -- OUT
ssp_reset => ssp_reset_i, -- OUT
tran_delay_meas => tran_delay_meas_i, -- OUT
tran_valid => tran_valid_i, -- OUT
......@@ -887,6 +886,12 @@ begin
RECESSIVE when (drv_bus_mon_ena = '1') else
bst_data_out;
----------------------------------------------------------------------------
-- Node transmitting dominant bit does shall not re-synchronize as a result
-- of dominant transmitted bit.
----------------------------------------------------------------------------
no_pos_resync <= '1' when (tx_data_wbs_i = DOMINANT) else
'0';
----------------------------------------------------------------------------
-- STATUS Bus Implementation
......
......@@ -379,9 +379,6 @@ entity protocol_control is
-- Resynchronisation
sync_control :out std_logic_vector(1 downto 0);
-- No Resynchronisation due to positive phase error
no_pos_resync :out std_logic;
-- Clear the Shift register for secondary sampling point.
ssp_reset :out std_logic;
......@@ -800,7 +797,6 @@ begin
nbt_ctrs_en => nbt_ctrs_en, -- OUT
dbt_ctrs_en => dbt_ctrs_en, -- OUT
sync_control => sync_control, -- OUT
no_pos_resync => no_pos_resync, -- OUT
ssp_reset => ssp_reset, -- OUT
tran_delay_meas => tran_delay_meas, -- OUT
tran_valid => tran_valid, -- OUT
......
......@@ -488,9 +488,6 @@ entity protocol_control_fsm is
-- Resynchronisation)
sync_control :out std_logic_vector(1 downto 0);
-- No Resynchronisation due to positive phase error
no_pos_resync :out std_logic;
-- Clear the Shift register for secondary sampling point.
ssp_reset :out std_logic;
......@@ -2907,11 +2904,6 @@ begin
else
'0';
-- No positive resynchronisation for transmitter of dominant bit!
no_pos_resync <= '1' when (is_transmitter = '1' and tx_data_wbs = DOMINANT)
else
'0';
rx_clear <= '1' when (rx_clear_i = '1' and rx_trigger = '1')
else
'0';
......
......@@ -1870,9 +1870,6 @@ package can_components is
-- Resynchronisation)
sync_control :out std_logic_vector(1 downto 0);
-- No Resynchronisation due to positive phase error
no_pos_resync :out std_logic;
-- Clear the Shift register for secondary sampling point.
ssp_reset :out std_logic;
......@@ -2224,9 +2221,6 @@ package can_components is
-- Resynchronisation
sync_control :out std_logic_vector(1 downto 0);
-- No Resynchronisation due to positive phase error
no_pos_resync :out std_logic;
-- Clear the Shift register for secondary sampling point.
ssp_reset :out std_logic;
......
......@@ -252,7 +252,6 @@ architecture Protocol_Control_unit_test of CAN_test is
-- Control signals
signal sp_control_1 : std_logic_vector(1 downto 0);
signal sync_control_1 : std_logic_vector(1 downto 0);
signal no_pos_resync_1 : std_logic;
signal ssp_reset_1 : std_logic;
signal tran_delay_meas_1 : std_logic;
signal tran_valid_1 : std_logic;
......@@ -360,7 +359,6 @@ architecture Protocol_Control_unit_test of CAN_test is
-- Control signals
signal sp_control_2 : std_logic_vector(1 downto 0);
signal sync_control_2 : std_logic_vector(1 downto 0);
signal no_pos_resync_2 : std_logic;
signal ssp_reset_2 : std_logic;
signal tran_delay_meas_2 : std_logic;
signal tran_valid_2 : std_logic;
......@@ -760,7 +758,6 @@ begin
-- Control signals
sp_control => sp_control_1,
sync_control => sync_control_1,
no_pos_resync => no_pos_resync_1,
ssp_reset => ssp_reset_1,
tran_delay_meas => tran_delay_meas_1,
tran_valid => tran_valid_1,
......@@ -880,7 +877,6 @@ begin
-- Control signals
sp_control => sp_control_2,
sync_control => sync_control_2,
no_pos_resync => no_pos_resync_2,
ssp_reset => ssp_reset_2,
tran_delay_meas => tran_delay_meas_2,
tran_valid => tran_valid_2,
......
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