Commit 091e6489 authored by Ille, Ondrej, Ing.'s avatar Ille, Ondrej, Ing.

Merge branch '296-reduce-log-size' into 'master'

Resolve "reduce log size"

Closes #296

See merge request !249
parents 39f4a898 1a2cdc19
Pipeline #9603 passed with stage
in 15 seconds
......@@ -4,13 +4,13 @@ source_list:
vhdl_file: "../src/bus_sampling/bus_sampling.vhd"
lyx_output: "../doc/core/entity_docs/bus_sampling.lyx"
fault_confinement:
vhdl_file: "../src/can_core/fault_confinement/fault_confinement.vhd"
vhdl_file: "../src/can_core/fault_confinement.vhd"
lyx_output: "../doc/core/entity_docs/fault_confinement.lyx"
protocol_control:
vhdl_file: "../src/can_core/protocol_control/protocol_control.vhd"
vhdl_file: "../src/can_core/protocol_control.vhd"
lyx_output: "../doc/core/entity_docs/protocol_control.lyx"
protocol_control_fsm:
vhdl_file: "../src/can_core/protocol_control/protocol_control_fsm.vhd"
vhdl_file: "../src/can_core/protocol_control_fsm.vhd"
lyx_output: "../doc/core/entity_docs/protocol_control_fsm.lyx"
can_core:
vhdl_file: "../src/can_core/can_core.vhd"
......@@ -19,16 +19,16 @@ source_list:
vhdl_file: "../src/can_top_level.vhd"
lyx_output: "../doc/core/entity_docs/can_top_level.lyx"
operation_control:
vhdl_file: "../src/can_core/operation_control/operation_control.vhd"
vhdl_file: "../src/can_core/operation_control.vhd"
lyx_output: "../doc/core/entity_docs/operation_control.lyx"
bit_stuffing:
vhdl_file: "../src/can_core/bit_stuffing/bit_stuffing.vhd"
vhdl_file: "../src/can_core/bit_stuffing.vhd"
lyx_output: "../doc/core/entity_docs/bit_stuffing.lyx"
bit_destuffing:
vhdl_file: "../src/can_core/bit_destuffing/bit_destuffing.vhd"
vhdl_file: "../src/can_core/bit_destuffing.vhd"
lyx_output: "../doc/core/entity_docs/bit_destuffing.lyx"
can_crc:
vhdl_file: "../src/can_core/crc/can_crc.vhd"
vhdl_file: "../src/can_core/can_crc.vhd"
lyx_output: "../doc/core/entity_docs/can_crc.lyx"
prescaler:
vhdl_file: "../src/prescaler/prescaler.vhd"
......
This diff is collapsed.
......@@ -380,8 +380,6 @@ begin
-- Assertions
------------------------------------------------------------------------------
-- psl default clock is rising_edge(clk_sys);
--
------------------------------------------------------------------------------
-- Functional coverage
......@@ -389,7 +387,6 @@ begin
--
-- psl txt_buf_wait_till_timestamp_cov : cover
-- (curr_state = s_arb_sel_upp_ts and fsm_wait_state_q = '0' and
-- timestamp_valid = '0')
-- report "TXT Buffer waiting for Timestamp to reach TX Time";
-- timestamp_valid = '0');
end architecture;
\ No newline at end of file
end architecture;
......@@ -47,7 +47,7 @@ feature:
arbitration:
fault_confinement:
forbid_fd:
interrupt:
# interrupt:
int_rx:
int_tx:
int_ewl:
......@@ -67,11 +67,11 @@ feature:
timestamp_options:
byte_enable:
data_length_code:
bus_start:
# bus_start:
data_overrun_clear:
iterations: 1
txtb_state:
iterations: 1
# txtb_state:
# iterations: 1
message_filter:
iterations: 1
timestamp_registers:
......
......@@ -73,7 +73,7 @@ feature:
arbitration:
fault_confinement:
forbid_fd:
interrupt:
# interrupt:
int_rx:
int_tx:
int_ewl:
......@@ -93,11 +93,11 @@ feature:
timestamp_options:
byte_enable:
data_length_code:
bus_start:
# bus_start:
data_overrun_clear:
iterations: 1
txtb_state:
iterations: 1
#txtb_state:
# iterations: 1
message_filter:
iterations: 1
timestamp_registers:
......
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