Commit 08960454 authored by Ille, Ondrej, Ing.'s avatar Ille, Ondrej, Ing.

Merge branch '205-ssp-offset-feature-test' into 'master'

doc: Fix datasheet link

Closes #205

See merge request !311
parents 72ab7315 4b68c064
Pipeline #14494 failed with stages
in 76 minutes and 46 seconds
...@@ -22,7 +22,7 @@ Architecture of CTU CAN FD is described in: ...@@ -22,7 +22,7 @@ Architecture of CTU CAN FD is described in:
[![System architecture](https://img.shields.io/badge/System_architecture--blue.svg)]( http://canbus.pages.fel.cvut.cz/ctucanfd_ip_core/ctu_can_fd_architecture.pdf) [![System architecture](https://img.shields.io/badge/System_architecture--blue.svg)]( http://canbus.pages.fel.cvut.cz/ctucanfd_ip_core/ctu_can_fd_architecture.pdf)
Functional description of CTU CAN FD is in datasheet: Functional description of CTU CAN FD is in datasheet:
[![Datasheet](https://img.shields.io/badge/Datasheet--blue.svg)]( http://canbus.pages.fel.cvut.cz/ctucanfd_ip_core/ProgDokum.pdf) [![Datasheet](https://img.shields.io/badge/Datasheet--blue.svg)]( http://canbus.pages.fel.cvut.cz/ctucanfd_ip_core/Progdokum.pdf)
CTU CAN FD is written with frequent usage of clock enables (FPGA) allowing inferred clock gating. CTU CAN FD is written with frequent usage of clock enables (FPGA) allowing inferred clock gating.
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