Commit 06926288 authored by Ille, Ondrej, Ing.'s avatar Ille, Ondrej, Ing.

Brought up transceiver delay feature test.

parent 2f9b1618
......@@ -37,21 +37,20 @@
--------------------------------------------------------------------------------
-- Purpose:
--
-- Transceiver delay compensation feature test.
--
-- Test sequence is like so:
-- 1.
-- 2.
-- 3.
-- 4.
-- 5.
-- 6.
-- 1. Generate random CAN FD Frame with BRS.
-- 2. Send frame on the bus.
-- 3. Wait unil frame is sent.
-- 4. Read value of transceiver delay and check if it is matching constant
-- value set in environment.
--
--------------------------------------------------------------------------------
-- Revision History:
--
-- 28.6.2016 Created file
--
-- 12.6.2018 Changed to use CAN test lib instead of direct register access.
--------------------------------------------------------------------------------
Library ieee;
......@@ -67,69 +66,68 @@ use work.CAN_FD_frame_format.all;
package tran_delay_feature is
procedure tran_delay_feature_exec(
variable outcome : inout boolean;
signal rand_ctr :inout natural range 0 to RAND_POOL_SIZE;
signal mem_bus_1 :inout Avalon_mem_type;
signal mem_bus_2 :inout Avalon_mem_type;
--Additional signals for tests
--Pretty much everything can be read out of stat bus...
signal bus_level :in std_logic;
signal drv_bus_1 :in std_logic_vector(1023 downto 0);
signal drv_bus_2 :in std_logic_vector(1023 downto 0);
signal stat_bus_1 :in std_logic_vector(511 downto 0);
signal stat_bus_2 :in std_logic_vector(511 downto 0)
);
procedure tran_delay_feature_exec(
variable outcome : inout boolean;
signal rand_ctr : inout natural range 0 to RAND_POOL_SIZE;
signal mem_bus_1 : inout Avalon_mem_type;
signal mem_bus_2 : inout Avalon_mem_type;
signal bus_level : in std_logic;
signal drv_bus_1 : in std_logic_vector(1023 downto 0);
signal drv_bus_2 : in std_logic_vector(1023 downto 0);
signal stat_bus_1 : in std_logic_vector(511 downto 0);
signal stat_bus_2 : in std_logic_vector(511 downto 0)
);
end package;
package body tran_delay_feature is
procedure tran_delay_feature_exec(
variable outcome : inout boolean;
signal rand_ctr :inout natural range 0 to RAND_POOL_SIZE;
signal mem_bus_1 :inout Avalon_mem_type;
signal mem_bus_2 :inout Avalon_mem_type;
--Additional signals for tests
--Pretty much everything can be read out of stat bus...
signal bus_level :in std_logic;
signal drv_bus_1 :in std_logic_vector(1023 downto 0);
signal drv_bus_2 :in std_logic_vector(1023 downto 0);
signal stat_bus_1 :in std_logic_vector(511 downto 0);
signal stat_bus_2 :in std_logic_vector(511 downto 0)
)is
variable r_data : std_logic_vector(31 downto 0):=(OTHERS => '0');
variable w_data : std_logic_vector(31 downto 0):=(OTHERS => '0');
variable ID_1 : natural:=1;
variable ID_2 : natural:=2;
variable CAN_frame : SW_CAN_frame_type;
variable frame_sent : boolean:=false;
variable delay : natural;
begin
outcome:=true;
----------------------------------------------
--Generate CAN frame
----------------------------------------------
CAN_generate_frame(rand_ctr,CAN_frame);
CAN_frame.rtr:= NO_RTR_FRAME;
CAN_frame.frame_format:= FD_CAN;
CAN_frame.brs:=BR_SHIFT;
CAN_send_frame(CAN_frame,1,ID_1,mem_bus_1,frame_sent);
CAN_wait_frame_sent(ID_2,mem_bus_2);
-----------------------------------------------------
-- Read the transciever delay compensation register
-----------------------------------------------------
CAN_read(r_data,TRV_DELAY_ADR,ID_1,mem_bus_1);
delay:=to_integer(unsigned(r_data));
--If delay is not matching the environment set delay
if(delay /= 22)then
outcome:=false;
end if;
procedure tran_delay_feature_exec(
variable outcome : inout boolean;
signal rand_ctr : inout natural range 0 to RAND_POOL_SIZE;
signal mem_bus_1 : inout Avalon_mem_type;
signal mem_bus_2 : inout Avalon_mem_type;
signal bus_level : in std_logic;
signal drv_bus_1 : in std_logic_vector(1023 downto 0);
signal drv_bus_2 : in std_logic_vector(1023 downto 0);
signal stat_bus_1 : in std_logic_vector(511 downto 0);
signal stat_bus_2 : in std_logic_vector(511 downto 0)
)is
variable r_data : std_logic_vector(31 downto 0) :=
(OTHERS => '0');
variable w_data : std_logic_vector(31 downto 0) :=
(OTHERS => '0');
variable ID_1 : natural := 1;
variable ID_2 : natural := 2;
variable CAN_frame : SW_CAN_frame_type;
variable frame_sent : boolean := false;
variable delay : natural;
begin
outcome := true;
------------------------------------------------------------------------
-- Generate CAN frame
------------------------------------------------------------------------
CAN_generate_frame(rand_ctr, CAN_frame);
CAN_frame.rtr := NO_RTR_FRAME;
CAN_frame.frame_format := FD_CAN;
CAN_frame.brs := BR_SHIFT;
CAN_send_frame(CAN_frame, 1, ID_1, mem_bus_1, frame_sent);
CAN_wait_frame_sent(ID_2, mem_bus_2);
------------------------------------------------------------------------
-- Read the transciever delay compensation register
------------------------------------------------------------------------
read_trv_delay(delay, ID_1, mem_bus_1);
------------------------------------------------------------------------
-- Check if delay is matching environment transceiver delay...
-- Note, that 2 DFFs sync. chain must be taken into account
------------------------------------------------------------------------
if (delay /= 22) then
outcome := false;
end if;
end procedure;
......
......@@ -1419,6 +1419,22 @@ package CANtestLib is
);
----------------------------------------------------------------------------
-- Read transceiver delay register.
--
-- Arguments:
-- ctr Variable in which traffic counters will be stored
-- ID Index of CTU CAN FD Core instance.
-- mem_bus Avalon memory bus to execute the access on.
----------------------------------------------------------------------------
procedure read_trv_delay(
variable trv_delay : out natural;
constant ID : in natural range 0 to 15;
signal mem_bus : inout Avalon_mem_type
);
----------------------------------------------------------------------------
----------------------------------------------------------------------------
-- sanity test Stuff; must be in a package
......@@ -3450,6 +3466,18 @@ package body CANtestLib is
end procedure;
procedure read_trv_delay(
variable trv_delay : out natural;
constant ID : in natural range 0 to 15;
signal mem_bus : inout Avalon_mem_type
)is
variable data : std_logic_vector(31 downto 0);
begin
CAN_read(data, TRV_DELAY_ADR, ID, mem_bus);
trv_delay := to_integer(unsigned(data(
TRV_DELAY_VALUE_H downto TRV_DELAY_VALUE_L)));
end procedure;
end package body;
......
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