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C
CTU CAN FD IP Core
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canbus
CTU CAN FD IP Core
Commits
058af19a
Commit
058af19a
authored
Jun 16, 2018
by
Martin Jeřábek
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fix feature test wave file for new hierarchy
parent
3af861d9
Changes
4
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4 changed files
with
45 additions
and
25 deletions
+45
-25
test/feature/feature_env_setup.tcl
test/feature/feature_env_setup.tcl
+26
-22
test/testfw/test_feature.py
test/testfw/test_feature.py
+14
-1
test/testfw/test_unit.py
test/testfw/test_unit.py
+4
-2
test/tests_fast.yml
test/tests_fast.yml
+1
-0
No files found.
test/feature/feature_env_setup.tcl
View file @
058af19a
...
@@ -39,10 +39,14 @@
...
@@ -39,10 +39,14 @@
################################################################################
################################################################################
global TCOMP
global TCOMP
global INST1
global INST1
global SIG1
global SIG2
global CORE
global CORE
start_CAN_simulation
"feature_env_test_wrapper"
start_CAN_simulation
"feature_env_test_wrapper"
quietly set INST1
"can_inst_1"
quietly set INST1
"g_inst(1)/can_inst"
quietly set SIG1
"p(1)"
quietly set SIG2
"p(2)"
quietly set CORE
"core_top_comp"
quietly set CORE
"core_top_comp"
################################################################################
################################################################################
...
@@ -57,12 +61,12 @@ add wave -label "Name of test" $TCOMP/test_name
...
@@ -57,12 +61,12 @@ add wave -label "Name of test" $TCOMP/test_name
#Add circuit specific signals
#Add circuit specific signals
add wave -noupdate -divider -height 20
"System and CAN bus"
add wave -noupdate -divider -height 20
"System and CAN bus"
add wave -label
"Node 1 clock"
$TCOMP/
clk_sys_1
add wave -label
"Node 1 clock"
$TCOMP/
$SIG1.clk_sys
add wave -label
"Node 2 clock"
$TCOMP/
clk_sys_2
add wave -label
"Node 2 clock"
$TCOMP/
$SIG2.clk_sys
add wave -label
"Node 1 reset"
$TCOMP/
res_n_1
add wave -label
"Node 1 reset"
$TCOMP/
$SIG1.res_n
add wave -label
"Node 2 reset"
$TCOMP/
res_n_2
add wave -label
"Node 2 reset"
$TCOMP/
$SIG2.res_n
add wave -label
"Timestamp 1"
$TCOMP/
timestamp_1
add wave -label
"Timestamp 1"
$TCOMP/
$SIG1.timestamp
add wave -label
"Timestamp 2"
$TCOMP/
timestamp_2
add wave -label
"Timestamp 2"
$TCOMP/
$SIG2.timestamp
add wave -label
"Bus level"
$TCOMP/bus_level
add wave -label
"Bus level"
$TCOMP/bus_level
add wave -label
"Inject to bus"
$TCOMP/bl_force
add wave -label
"Inject to bus"
$TCOMP/bl_force
add wave -label
"Value to inject"
$TCOMP/bl_inject
add wave -label
"Value to inject"
$TCOMP/bl_inject
...
@@ -70,11 +74,11 @@ add wave -label "Value to inject" $TCOMP/bl_inject
...
@@ -70,11 +74,11 @@ add wave -label "Value to inject" $TCOMP/bl_inject
add wave -noupdate -divider -height 20
"Node 1"
add wave -noupdate -divider -height 20
"Node 1"
add wave -label
"Memory bus"
$TCOMP/mem_bus_1
add wave -label
"Memory bus"
"
$
TCOMP/mem_bus(1)"
add wave -label
"CAN_TX"
$TCOMP/
can_tx_1
add wave -label
"CAN_TX"
$TCOMP/
$SIG1.can_tx
add wave -label
"CAN_RX"
$TCOMP/
can_rx_1
add wave -label
"CAN_RX"
$TCOMP/
$SIG1.can_rx
add wave -label
"Interrupt"
$TCOMP/
int_1
add wave -label
"Interrupt"
$TCOMP/
$SIG1.int
add wave -label
"Transc
iever delay"
$TCOMP/tr_del_1
add wave -label
"Transc
eiver delay"
$TCOMP/$SIG1.tr_del
add wave -label
"Driving bus"
$TCOMP/$INST1/drv_bus
add wave -label
"Driving bus"
$TCOMP/$INST1/drv_bus
add wave -label
"Status bus"
$TCOMP/$INST1/stat_bus
add wave -label
"Status bus"
$TCOMP/$INST1/stat_bus
...
@@ -162,8 +166,8 @@ add wave -group "CAN Core (1)" \
...
@@ -162,8 +166,8 @@ add wave -group "CAN Core (1)" \
-label
"Stuff counter"
$TCOMP/$INST1/$CORE/st_ctr_resolved
-label
"Stuff counter"
$TCOMP/$INST1/$CORE/st_ctr_resolved
add wave -group
"Bus sampling (1)"
\
add wave -group
"Bus sampling (1)"
\
-label
"Measure transc
ie
ver delay"
$TCOMP/$INST1/trv_delay_calib
\
-label
"Measure transc
ei
ver delay"
$TCOMP/$INST1/trv_delay_calib
\
-label
"Transc
ie
ver delay"
$TCOMP/$INST1/bus_sync_comp/trv_delay
\
-label
"Transc
ei
ver delay"
$TCOMP/$INST1/bus_sync_comp/trv_delay
\
-label
"Measurment running"
$TCOMP/$INST1/bus_sync_comp/trv_running
\
-label
"Measurment running"
$TCOMP/$INST1/bus_sync_comp/trv_running
\
-label
"Reset secondary sampling"
$TCOMP/$INST1/ssp_reset
\
-label
"Reset secondary sampling"
$TCOMP/$INST1/ssp_reset
\
-label
"Bit error secondary sampling"
$TCOMP/$INST1/bit_error_sec_sam
\
-label
"Bit error secondary sampling"
$TCOMP/$INST1/bit_error_sec_sam
\
...
@@ -172,13 +176,13 @@ add wave -group "Bus sampling (1)" \
...
@@ -172,13 +176,13 @@ add wave -group "Bus sampling (1)" \
add wave -noupdate -divider -height 20
"Node 2"
add wave -noupdate -divider -height 20
"Node 2"
quietly set INST1
"
can_inst_2
"
quietly set INST1
"
g_inst(2)/can_inst
"
add wave -label
"Memory bus"
$TCOMP/mem_bus_2
add wave -label
"Memory bus"
"
$
TCOMP/mem_bus(2)"
add wave -label
"CAN_TX"
$TCOMP/
can_tx_2
add wave -label
"CAN_TX"
$TCOMP/
$SIG2.can_tx
add wave -label
"CAN_RX"
$TCOMP/
can_rx_2
add wave -label
"CAN_RX"
$TCOMP/
$SIG2.can_rx
add wave -label
"Interrupt"
$TCOMP/
int_2
add wave -label
"Interrupt"
$TCOMP/
$SIG2.int
add wave -label
"Transc
iever delay"
$TCOMP/tr_del_2
add wave -label
"Transc
eiver delay"
$TCOMP/$SIG2.tr_del
add wave -label
"Driving bus"
$TCOMP/$INST1/drv_bus
add wave -label
"Driving bus"
$TCOMP/$INST1/drv_bus
add wave -label
"Status bus"
$TCOMP/$INST1/stat_bus
add wave -label
"Status bus"
$TCOMP/$INST1/stat_bus
...
@@ -260,8 +264,8 @@ add wave -group "CAN Core (2)" \
...
@@ -260,8 +264,8 @@ add wave -group "CAN Core (2)" \
-label
"Stuff counter"
$TCOMP/$INST1/$CORE/st_ctr_resolved
-label
"Stuff counter"
$TCOMP/$INST1/$CORE/st_ctr_resolved
add wave -group
"Bus sampling (2)"
\
add wave -group
"Bus sampling (2)"
\
-label
"Measure transc
ie
ver delay"
$TCOMP/$INST1/trv_delay_calib
\
-label
"Measure transc
ei
ver delay"
$TCOMP/$INST1/trv_delay_calib
\
-label
"Transc
ie
ver delay"
$TCOMP/$INST1/bus_sync_comp/trv_delay
\
-label
"Transc
ei
ver delay"
$TCOMP/$INST1/bus_sync_comp/trv_delay
\
-label
"Measurment running"
$TCOMP/$INST1/bus_sync_comp/trv_running
\
-label
"Measurment running"
$TCOMP/$INST1/bus_sync_comp/trv_running
\
-label
"Reset secondary sampling"
$TCOMP/$INST1/ssp_reset
\
-label
"Reset secondary sampling"
$TCOMP/$INST1/ssp_reset
\
-label
"Bit error secondary sampling"
$TCOMP/$INST1/bit_error_sec_sam
\
-label
"Bit error secondary sampling"
$TCOMP/$INST1/bit_error_sec_sam
\
...
...
test/testfw/test_feature.py
View file @
058af19a
import
logging
import
logging
from
pathlib
import
Path
from
pathlib
import
Path
from
.test_common
import
add_sources
,
TestsBase
,
dict_merge
,
vhdl_serialize
from
.test_common
import
add_sources
,
TestsBase
,
dict_merge
,
get_common_modelsim_init_files
from
textwrap
import
dedent
log
=
logging
.
getLogger
(
__name__
)
log
=
logging
.
getLogger
(
__name__
)
...
@@ -27,6 +28,18 @@ class FeatureTests(TestsBase):
...
@@ -27,6 +28,18 @@ class FeatureTests(TestsBase):
tb
=
self
.
lib
.
get_test_benches
(
'*tb_feature'
)[
0
]
tb
=
self
.
lib
.
get_test_benches
(
'*tb_feature'
)[
0
]
default
=
self
.
config
[
'default'
]
default
=
self
.
config
[
'default'
]
self
.
add_modelsim_gui_file
(
tb
,
default
,
'feature'
)
self
.
add_modelsim_gui_file
(
tb
,
default
,
'feature'
)
# generate & set per-test modelsim tcl file
tcl
=
self
.
build
/
'modelsim_init_feature.tcl'
with
tcl
.
open
(
'wt'
,
encoding
=
'utf-8'
)
as
f
:
print
(
dedent
(
'''
\
global TCOMP
set TCOMP tb_feature/test_comp
'''
),
file
=
f
)
init_files
=
get_common_modelsim_init_files
()
init_files
+=
[
str
(
tcl
)]
tb
.
set_sim_option
(
"modelsim.init_files.after_load"
,
init_files
)
for
name
,
cfg
in
self
.
config
[
'tests'
].
items
():
for
name
,
cfg
in
self
.
config
[
'tests'
].
items
():
if
cfg
is
None
:
if
cfg
is
None
:
cfg
=
dict
()
cfg
=
dict
()
...
...
test/testfw/test_unit.py
View file @
058af19a
import
re
import
re
import
logging
import
logging
from
textwrap
import
dedent
from
textwrap
import
dedent
from
.test_common
import
*
from
.test_common
import
add_sources
,
dict_merge
,
TestsBase
,
get_common_modelsim_init_files
from
pprint
import
pprint
log
=
logging
.
getLogger
(
__name__
)
log
=
logging
.
getLogger
(
__name__
)
class
UnitTests
(
TestsBase
):
class
UnitTests
(
TestsBase
):
def
add_sources
(
self
):
def
add_sources
(
self
):
add_sources
(
self
.
lib
,
[
'unit/**/*.vhd'
])
add_sources
(
self
.
lib
,
[
'unit/**/*.vhd'
])
self
.
_create_wrapper
(
self
.
build
/
"tb_wrappers.vhd"
)
self
.
_create_wrapper
(
self
.
build
/
"tb_wrappers.vhd"
)
def
configure
(
self
):
def
configure
(
self
):
ui
,
lib
,
config
,
build
=
self
.
ui
,
self
.
lib
,
self
.
config
,
self
.
build
lib
,
config
,
build
=
self
.
lib
,
self
.
config
,
self
.
build
default
=
config
[
'default'
]
default
=
config
[
'default'
]
unit_tests
=
lib
.
get_test_benches
(
'*_unit_test'
)
unit_tests
=
lib
.
get_test_benches
(
'*_unit_test'
)
for
name
,
cfg
in
config
[
'tests'
].
items
():
for
name
,
cfg
in
config
[
'tests'
].
items
():
...
...
test/tests_fast.yml
View file @
058af19a
...
@@ -37,6 +37,7 @@ feature:
...
@@ -37,6 +37,7 @@ feature:
error_tolerance
:
0
error_tolerance
:
0
iterations
:
1
iterations
:
1
timeout
:
1 ms
timeout
:
1 ms
wave
:
feature/feature_env_setup.tcl
tests
:
tests
:
abort_transmittion
:
abort_transmittion
:
arbitration
:
arbitration
:
...
...
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