Commit 01dca836 authored by Ille, Ondrej, Ing.'s avatar Ille, Ondrej, Ing.

Merge branch '355-fix-rec-decrement' into 'master'

Resolve "Fix REC decrement"

Closes #355

See merge request !336
parents 752f996d 151488aa
Pipeline #19108 passed with stage
in 19 seconds
......@@ -366,7 +366,6 @@ architecture rtl of can_core is
signal tran_delay_meas_i : std_logic;
signal tran_valid_i : std_logic;
signal rec_valid_i : std_logic;
signal ack_received_i : std_logic;
signal br_shifted_i : std_logic;
-- Fault confinement status signals
......@@ -446,6 +445,9 @@ architecture rtl of can_core is
signal retr_ctr_i : std_logic_vector(G_RETR_LIM_CTR_WIDTH - 1 downto 0);
-- Decrement Receive Error counter
signal decrement_rec : std_logic;
begin
----------------------------------------------------------------------------
......@@ -580,9 +582,9 @@ begin
tran_delay_meas => tran_delay_meas_i, -- OUT
tran_valid => tran_valid_i, -- OUT
rec_valid => rec_valid_i, -- OUT
decrement_rec => decrement_rec, -- OUT
-- Status signals
ack_received => ack_received_i, -- OUT
br_shifted => br_shifted_i, -- OUT
form_err => form_err, -- OUT
ack_err => ack_err, -- OUT
......@@ -654,6 +656,7 @@ begin
err_delim_late => err_delim_late, -- IN
tran_valid => tran_valid_i, -- IN
rec_valid => rec_valid_i, -- IN
decrement_rec => decrement_rec, -- IN
-- Fault confinement State indication
is_err_active => is_err_active, -- OUT
......@@ -895,6 +898,7 @@ begin
stat_bus(113) <= '0';
stat_bus(115) <= '0';
stat_bus(183) <= '0';
stat_bus(255) <= '0';
stat_bus(120 downto 118) <= (OTHERS => '0');
stat_bus(178 downto 158) <= (OTHERS => '0');
......@@ -1129,9 +1133,6 @@ begin
stat_bus(STAT_ERR_VALID_INDEX) <=
err_detected_i;
stat_bus(STAT_ACK_RECIEVED_OUT_INDEX) <=
ack_received_i;
stat_bus(STAT_BIT_ERR_VALID_INDEX) <=
bit_err;
......
......@@ -134,6 +134,9 @@ entity fault_confinement is
-- Reception of frame valid
rec_valid :in std_logic;
-- Decrement receive Error counter
decrement_rec :in std_logic;
-----------------------------------------------------------------------
-- Fault confinement State indication
......@@ -278,7 +281,7 @@ begin
act_err_ovr_flag => act_err_ovr_flag, -- IN
err_delim_late => err_delim_late, -- IN
tran_valid => tran_valid, -- IN
rec_valid => rec_valid, -- IN
decrement_rec => decrement_rec, -- IN
inc_one => inc_one, -- OUT
inc_eight => inc_eight, -- OUT
......
......@@ -97,8 +97,8 @@ entity fault_confinement_rules is
-- Transmission of frame valid
tran_valid :in std_logic;
-- Reception of frame valid
rec_valid :in std_logic;
-- Decrement receive Error counter
decrement_rec :in std_logic;
-----------------------------------------------------------------------
-- Output signals to error counters
......@@ -150,7 +150,7 @@ begin
---------------------------------------------------------------------------
-- Decrement by 1 when either transmission or reception is valid
---------------------------------------------------------------------------
dec_one <= '1' when (rec_valid = '1' or tran_valid = '1') else
dec_one <= '1' when (decrement_rec = '1' or tran_valid = '1') else
'0';
end architecture;
......@@ -393,13 +393,13 @@ entity protocol_control is
-- Received frame is valid
rec_valid :out std_logic;
-- Decrement Receive Error counter
decrement_rec :out std_logic;
-----------------------------------------------------------------------
-- Status signals
-----------------------------------------------------------------------
-- ACK received
ack_received :out std_logic;
-- Bit rate shifted
br_shifted :out std_logic;
......@@ -788,7 +788,8 @@ begin
is_err_active => is_err_active, -- IN
is_err_passive => is_err_passive, -- IN
is_bus_off => is_bus_off, -- IN
decrement_rec => decrement_rec, -- OUT
-- Other control signals
sp_control => sp_control, -- OUT
sp_control_q => sp_control_q, -- OUT
......@@ -799,7 +800,6 @@ begin
ssp_reset => ssp_reset, -- OUT
tran_delay_meas => tran_delay_meas, -- OUT
tran_valid => tran_valid, -- OUT
ack_received => ack_received, -- OUT
crc_enable => crc_enable, -- OUT
crc_spec_enable => crc_spec_enable, -- OUT
crc_calc_from_rx => crc_calc_from_rx, -- OUT
......
......@@ -463,6 +463,9 @@ entity protocol_control_fsm is
-- Unit is Bus off
is_bus_off :in std_logic;
-- Decrement REC
decrement_rec :out std_logic;
-----------------------------------------------------------------------
-- Other control signals
-----------------------------------------------------------------------
......@@ -497,9 +500,6 @@ entity protocol_control_fsm is
-- Transmitted frame is valid
tran_valid :out std_logic;
-- ACK received
ack_received :out std_logic;
-- CRC calculation enabled
crc_enable :out std_logic;
......@@ -726,8 +726,9 @@ architecture rtl of protocol_control_fsm is
-- Increment Retransmitt counter by 1
signal retr_ctr_add_i : std_logic;
-- Decrement Receive error counter (internal value)
signal decrement_rec_i : std_logic;
-- Blocking register for retransmitt counter add signal.
signal retr_ctr_add_block : std_logic;
signal retr_ctr_add_block_clr : std_logic;
......@@ -1093,7 +1094,8 @@ begin
end if;
-------------------------------------------------------------------
-- Secondary CRC Delimiter, or an ACK Slot if DOMINANT.
-- Secondary CRC Delimiter (Transmitter of FD frame only), or an
-- ACK Slot if DOMINANT.
-------------------------------------------------------------------
when s_pc_crc_delim_sec =>
if (rx_data_nbs = DOMINANT) then
......@@ -1400,7 +1402,6 @@ begin
set_err_active_i <= '0';
br_shifted_i <= '0';
ack_received <= '0';
-- Bit Stuffing/Destuffing control
stuff_length <= std_logic_vector(to_unsigned(5, 3));
......@@ -1446,6 +1447,7 @@ begin
is_sof <= '0';
clr_bus_off_rst_flg <= '0';
decrement_rec_i <= '0';
if (err_frm_req = '1') then
tick_state_reg <= '1';
......@@ -2082,6 +2084,10 @@ begin
dbt_ctrs_en <= '1';
bit_err_disable <= '1';
-- Note: We don't have to consider decrement of REC here,
-- because we get here only for transmitter of CAN FD
-- frame!
-------------------------------------------------------------------
-- ACK Slot, or a ACK delim, if previous two bits were recessive!
-------------------------------------------------------------------
......@@ -2096,22 +2102,24 @@ begin
drv_ack_forb = '0')
then
tx_dominant <= '1';
-- Bit Error still shall be detected when unit sends dominant
-- (receiver) and receives recessive!
else
bit_err_disable <= '1';
end if;
if (is_receiver = '1' and crc_match = '1' and
rx_data_nbs = DOMINANT)
then
decrement_rec_i <= '1';
end if;
if (is_transmitter = '1' and drv_self_test_ena = '0' and
rx_data_nbs = RECESSIVE)
then
ack_err_i <= '1';
end if;
if (rx_data_nbs = DOMINANT) then
ack_received <= '1';
end if;
-------------------------------------------------------------------
-- Secondary ACK field (in FD Frames),or ACK Delimiter if RECESSIVE
......@@ -2132,10 +2140,6 @@ begin
crc_err_i <= '1';
end if;
if (rx_data_nbs = DOMINANT) then
ack_received <= '1';
end if;
-------------------------------------------------------------------
-- ACK Delimiter
-------------------------------------------------------------------
......@@ -2753,6 +2757,7 @@ begin
ack_err <= ack_err_i and rx_trigger;
crc_err <= crc_err_i and rx_trigger;
bit_err_arb <= bit_err_arb_i and rx_trigger;
decrement_rec <= decrement_rec_i and rx_trigger;
-----------------------------------------------------------------------
-- Switching of Bit-rate
......
......@@ -902,7 +902,7 @@ package can_components is
-- Unit is transmitter
is_transmitter :in std_logic;
-- Unit is receiver
is_receiver :in std_logic;
......@@ -1019,8 +1019,8 @@ package can_components is
-- Transmission of frame valid
tran_valid :in std_logic;
-- Reception of frame valid
rec_valid :in std_logic;
-- Decrement receive Error counter
decrement_rec :in std_logic;
-----------------------------------------------------------------------
-- Output signals to error counters
......@@ -1105,6 +1105,9 @@ package can_components is
-- Reception of frame valid
rec_valid :in std_logic;
-- Decrement receive Error counter
decrement_rec :in std_logic;
-----------------------------------------------------------------------
-- Fault confinement State indication
......@@ -1842,6 +1845,9 @@ package can_components is
-- Unit is Bus off
is_bus_off :in std_logic;
-- Decrement REC
decrement_rec :out std_logic;
-----------------------------------------------------------------------
-- Other control signals
-----------------------------------------------------------------------
......@@ -1876,9 +1882,6 @@ package can_components is
-- Transmitted frame is valid
tran_valid :out std_logic;
-- ACK received
ack_received :out std_logic;
-- CRC calculation enabled
crc_enable :out std_logic;
......@@ -2232,13 +2235,13 @@ package can_components is
-- Received frame is valid
rec_valid :out std_logic;
-- Decrement Receive Error counter
decrement_rec :out std_logic;
-----------------------------------------------------------------------
-- Status signals
-----------------------------------------------------------------------
-- ACK received
ack_received :out std_logic;
-- Bit rate shifted
br_shifted :out std_logic;
......
......@@ -371,8 +371,6 @@ package drv_stat_pkg is
constant STAT_EWL_REACHED_INDEX : natural := 253;
constant STAT_ERR_VALID_INDEX : natural := 254;
constant STAT_ACK_RECIEVED_OUT_INDEX : natural := 255;
constant STAT_BIT_ERR_VALID_INDEX : natural := 256;
constant STAT_BS_CTR_HIGH : natural := 302;
......
......@@ -259,7 +259,6 @@ architecture Protocol_Control_unit_test of CAN_test is
signal rec_valid_1 : std_logic;
-- Status signals
signal ack_received_1 : std_logic;
signal br_shifted_1 : std_logic;
signal form_err_1 : std_logic;
signal ack_err_1 : std_logic;
......@@ -368,7 +367,6 @@ architecture Protocol_Control_unit_test of CAN_test is
signal rec_valid_2 : std_logic;
-- Status signals
signal ack_received_2 : std_logic;
signal br_shifted_2 : std_logic;
signal form_err_2 : std_logic;
signal ack_err_2 : std_logic;
......@@ -769,7 +767,6 @@ begin
rec_valid => rec_valid_1,
-- Status signals
ack_received => ack_received_1,
br_shifted => br_shifted_1,
form_err => form_err_1,
ack_err => ack_err_1,
......@@ -890,7 +887,6 @@ begin
rec_valid => rec_valid_2,
-- Status signals
ack_received => ack_received_2,
br_shifted => br_shifted_2,
form_err => form_err_2,
ack_err => ack_err_2,
......
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