This is implemented to so that resynchronisation works properly
in case of bit-rate shift when there is resynchronisation edge
just next cycle after Sample point (in Process pipeline stage).

Single counter solution was reverted since adding it caused critical
timing paths and core got below 100 MHz. Trade of is sth like:
Two counters solution: + 50 LUTs, + DFFs, but better timing by
approx 2.5 ns Setup Slack.

So in the end we will stick with two counters solution, just fix
bug that was discovered by sp_control bypass to Process pipeline
stage.