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  • Ille, Ondrej, Ing.'s avatar
    src: Use CRC init vector loading controlled by Protocol control FSM. · 0f1153da
    Ille, Ondrej, Ing. authored
    Init vector is not loaded on by edge on enable but by PC FSM. This
    allows removing special mux on datapath in Bit-destuffing. Thanks
    to this, when H-sync edge occurs in Idle right in Process pipeline
    stage, unit properly samples recessive and not dominant and measures
    length of arbitration field properly.
    
    CRC Init vector is always loaded in situations:
    1. In Intermission (first or second bit), does not mind being loaded
       twice. Can't be loaded in third one since this can already be SOF
       and first bit of calculation might be executed.
    2. Transfer to Idle after integration or reintegration.
    
    Note that there is always intermission after every frame so we are
    sure that init vector will get loaded! Loading post re-integration
    and integration is done just to be sure it is loaded after unit
    just joins the bus.
    0f1153da