operationControl.vhd 8.5 KB
Newer Older
Ille, Ondrej, Ing.'s avatar
Ille, Ondrej, Ing. committed
1
--------------------------------------------------------------------------------
Ille, Ondrej, Ing.'s avatar
Ille, Ondrej, Ing. committed
2
-- 
Ille, Ondrej, Ing.'s avatar
Ille, Ondrej, Ing. committed
3 4
-- CTU CAN FD IP Core
-- Copyright (C) 2015-2018 Ondrej Ille <ondrej.ille@gmail.com>
Ille, Ondrej, Ing.'s avatar
Ille, Ondrej, Ing. committed
5
-- 
Ille, Ondrej, Ing.'s avatar
Ille, Ondrej, Ing. committed
6 7 8 9
-- Project advisors and co-authors: 
-- 	Jiri Novak <jnovak@fel.cvut.cz>
-- 	Pavel Pisa <pisa@cmp.felk.cvut.cz>
-- 	Martin Jerabek <jerabma7@fel.cvut.cz>
Ille, Ondrej, Ing.'s avatar
Ille, Ondrej, Ing. committed
10 11 12 13
-- Department of Measurement         (http://meas.fel.cvut.cz/)
-- Faculty of Electrical Engineering (http://www.fel.cvut.cz)
-- Czech Technical University        (http://www.cvut.cz/)
-- 
14
-- Permission is hereby granted, free of charge, to any person obtaining a copy 
Ille, Ondrej, Ing.'s avatar
Ille, Ondrej, Ing. committed
15 16 17 18 19 20
-- of this VHDL component and associated documentation files (the "Component"), 
-- to deal in the Component without restriction, including without limitation 
-- the rights to use, copy, modify, merge, publish, distribute, sublicense, 
-- and/or sell copies of the Component, and to permit persons to whom the 
-- Component is furnished to do so, subject to the following conditions:
-- 
21
-- The above copyright notice and this permission notice shall be included in 
Ille, Ondrej, Ing.'s avatar
Ille, Ondrej, Ing. committed
22 23 24
-- all copies or substantial portions of the Component.
-- 
-- THE COMPONENT IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 
25 26 27 28
-- IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 
-- FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE 
-- AUTHORS OR COPYRIGHTHOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 
-- LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
Ille, Ondrej, Ing.'s avatar
Ille, Ondrej, Ing. committed
29 30 31
-- FROM, OUT OF OR IN CONNECTION WITH THE COMPONENT OR THE USE OR OTHER DEALINGS 
-- IN THE COMPONENT.
-- 
32 33 34
-- The CAN protocol is developed by Robert Bosch GmbH and protected by patents. 
-- Anybody who wants to implement this IP core on silicon has to obtain a CAN 
-- protocol license from Bosch.
Ille, Ondrej, Ing.'s avatar
Ille, Ondrej, Ing. committed
35
-- 
Ille, Ondrej, Ing.'s avatar
Ille, Ondrej, Ing. committed
36
--------------------------------------------------------------------------------
37

Ille, Ondrej, Ing.'s avatar
Ille, Ondrej, Ing. committed
38
--------------------------------------------------------------------------------
39
-- Purpose:
Ille, Ondrej, Ing.'s avatar
Ille, Ondrej, Ing. committed
40 41 42 43 44 45
--  Operation control state machine, handling whenever unit is Transciever, 
--  Reciever, Bus is idle or Integrating. Simple logic implemented for integra-
--  ting and possible to set machine into transciever or reciever state by 
--  set_transciever, set_reciever signals. (in start of frame, lost of 
--  arbitration)
--------------------------------------------------------------------------------
46 47
-- Revision History:
--    June 2015  Created file
48 49 50 51
--    30.8.2018  Pulled Operational State to integrating as long as CAN Node
--               is disabled. This makes sure that after Node was turned off,
--               it needs to integrate for 11 recessive bits again, before
--               turning Transceiver or Receiver!
52 53 54 55 56 57
--------------------------------------------------------------------------------

Library ieee;
USE IEEE.std_logic_1164.all;
USE IEEE.numeric_std.ALL;
use work.CANconstants.all;
58
use work.CAN_FD_register_map.all;
59 60

entity operationControl is
61 62 63 64 65 66 67
    port(
        ------------------------------------------------------------------------
        -- Clock and reset
        ------------------------------------------------------------------------
        signal clk_sys              :in   std_logic; 
        signal res_n                :in   std_logic;

68
        -- Driving bus
69 70
        signal drv_bus              :in   std_logic_vector(1023 downto 0);

71
        -- Driving signals
72 73 74 75
        signal arbitration_lost     :in   std_logic;
        signal PC_State             :in   protocol_type;
        signal tran_data_valid_in   :in   std_logic;

76
        -- Set OP_State FSM into transciever state (Used at SOF)
77 78
        signal set_transciever      :in   std_logic; 

79
        -- Set OP_State FSM into reciever state
80 81 82 83
        signal set_reciever         :in   std_logic;

        signal is_idle              :in   std_logic; --Unit is idle

84 85
        signal unknown_OP_state     :out  std_logic;

86
        -- Bit time triggering signals
87 88 89 90 91
        signal tran_trig            :in   std_logic;
        signal rec_trig             :in   std_logic;

        signal data_rx              :in   std_logic;

92
        -- Status outputs
93
        signal OP_State             :out  oper_mode_type
94
    );
95 96 97 98

    ----------------------------------------------------------------------------
    -- Internal registers
    ----------------------------------------------------------------------------
99
    signal OP_State_r               :     oper_mode_type; -- Operational mode
100 101 102 103

    -- Counter to INTEGRATING_DURATION, to switch from integrating to bus idle
    signal integ_counter            :     natural range 0 to 11; 
    signal drv_ena                  :     std_logic;
104 105 106 107 108 109 110
    
end entity;


architecture rtl of operationControl is
begin
  
111 112 113
    -- Registers to output propagation
    OP_State                          <= OP_State_r;
    drv_ena                           <= drv_bus(DRV_ENA_INDEX);
114
  
115 116 117 118 119
    OP_proc : process(clk_sys, res_n)
    begin
        if (res_n = ACT_RESET) then
            OP_State_r                    <= integrating;
            integ_counter                 <= 1;
120 121
            unknown_OP_state              <= '0';

122
        elsif rising_edge(clk_sys) then
123
            -- Presetting the registers to avoid latches
124 125
            OP_State_r                    <= OP_State_r;
            integ_counter                 <= integ_counter;
126
            unknown_OP_state              <= '0';
127

128 129 130 131

            if (drv_end /= ENABLED) then
                OP_State_r                <= integrating;
            elsif (set_transciever = '1') then
132
                OP_State_r                <= transciever;
Ille, Ondrej, Ing.'s avatar
Ille, Ondrej, Ing. committed
133
            elsif (set_reciever = '1') then
134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150
                OP_State_r                <= reciever;
            else
                case OP_State_r is

                ----------------------------------------------------------------
                -- Integrating
                -- Waiting for 11 consecutive recessive bits
                ----------------------------------------------------------------
                when integrating =>
                    if (drv_ena = ENABLED) then
                        if (rec_trig = '1') then
                            -- Counting up the integration period
                            if (integ_counter = INTEGRATING_DURATION) then
                                OP_State_r          <= idle;
                                integ_counter       <= 1;
                            else
                                if (data_rx = RECESSIVE) then 
Ille, Ondrej, Ing.'s avatar
Ille, Ondrej, Ing. committed
151
                                    integ_counter   <= integ_counter + 1;
152
                                else
Ille, Ondrej, Ing.'s avatar
Ille, Ondrej, Ing. committed
153
                                    integ_counter   <= 1;
154 155 156
                                end if;
                            end if;
                        end if;
157
                    else
Ille, Ondrej, Ing.'s avatar
Ille, Ondrej, Ing. committed
158 159
                        integ_counter      <= 1;
                        OP_State_r         <= OP_State_r;
160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183
                    end if;

                ----------------------------------------------------------------
                -- Idle
                -- Bus is idle, there is no frame in progress
                ----------------------------------------------------------------
                when idle =>
                    if (is_idle = '0') then
                        if (tran_trig = '1' and tran_data_valid_in = '1') then
                            OP_State_r        <= transciever;    
                        elsif (rec_trig = '1' and data_rx = DOMINANT) then
                            OP_State_r        <= reciever;
                        end if;
                    end if;

                ----------------------------------------------------------------
                -- Transceiver
                -- Unit is transmitter of a frame.
                ----------------------------------------------------------------
                when transciever =>
                    if (arbitration_lost = '1') then
                        OP_State_r          <= reciever;
                    elsif (is_idle = '1') then
                        OP_State_r          <= idle;
184
                    end if;
Ille, Ondrej, Ing.'s avatar
Ille, Ondrej, Ing. committed
185 186 187 188 189

                ----------------------------------------------------------------
                -- Receiver
                -- Unit is receiver of a frame.
                ----------------------------------------------------------------
190 191
                when reciever =>
                    if (is_idle = '1') then
Ille, Ondrej, Ing.'s avatar
Ille, Ondrej, Ing. committed
192
                        OP_State_r          <= idle;
193
                    end if;              
194
                when others =>
195
                    unknown_OP_state        <= '1';
196 197 198 199
                end case;
            end if;
        end if;
    end process;
200 201
  
end architecture;