can_core.vhd 47.7 KB
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--------------------------------------------------------------------------------
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-- 
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-- CTU CAN FD IP Core
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-- Copyright (C) 2015-2018
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-- 
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-- Authors:
--     Ondrej Ille <ondrej.ille@gmail.com>
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--     Martin Jerabek <martin.jerabek01@gmail.com>
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-- 
-- Project advisors: 
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-- 	Jiri Novak <jnovak@fel.cvut.cz>
-- 	Pavel Pisa <pisa@cmp.felk.cvut.cz>
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-- 
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-- Department of Measurement         (http://meas.fel.cvut.cz/)
-- Faculty of Electrical Engineering (http://www.fel.cvut.cz)
-- Czech Technical University        (http://www.cvut.cz/)
-- 
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-- Permission is hereby granted, free of charge, to any person obtaining a copy
-- of this VHDL component and associated documentation files (the "Component"),
-- to deal in the Component without restriction, including without limitation
-- the rights to use, copy, modify, merge, publish, distribute, sublicense,
-- and/or sell copies of the Component, and to permit persons to whom the
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-- Component is furnished to do so, subject to the following conditions:
-- 
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-- The above copyright notice and this permission notice shall be included in
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-- all copies or substantial portions of the Component.
-- 
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-- THE COMPONENT IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-- IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-- FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
-- AUTHORS OR COPYRIGHTHOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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-- LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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-- FROM, OUT OF OR IN CONNECTION WITH THE COMPONENT OR THE USE OR OTHER DEALINGS
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-- IN THE COMPONENT.
-- 
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-- The CAN protocol is developed by Robert Bosch GmbH and protected by patents.
-- Anybody who wants to implement this IP core on silicon has to obtain a CAN
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-- protocol license from Bosch.
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-- 
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--------------------------------------------------------------------------------

--------------------------------------------------------------------------------
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-- Module:
--  CAN Core
--
-- Sub-modules:
--   1. Protocol control
--   2. Bit stuffing
--   3. Bit destuffing
--   4. Fault confinement
--   5. CAN CRC
--   6. Operation control
--
--  Note:
--   Status bus assignments are implemented in this module.
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--------------------------------------------------------------------------------
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Library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.ALL;

Library work;
use work.id_transfer.all;
use work.can_constants.all;
use work.can_components.all;
use work.can_types.all;
use work.cmn_lib.all;
use work.drv_stat_pkg.all;
use work.reduce_lib.all;

use work.CAN_FD_register_map.all;
use work.CAN_FD_frame_format.all;
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entity can_core is
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    generic(
        -- Reset polarity
        G_RESET_POLARITY        :    std_logic := '0';
        
        -- Number of signals in Sample trigger
        G_SAMPLE_TRIGGER_COUNT  :   natural range 2 to 8 := 2;
        
        -- Control counter width
        G_CTRL_CTR_WIDTH        :     natural := 9;
        
        -- Retransmitt limit counter width
        G_RETR_LIM_CTR_WIDTH    :     natural := 4;
        
        -- Insert pipeline on "error_valid" 
        G_ERR_VALID_PIPELINE    :     boolean := true;
        
        -- CRC 15 polynomial
        G_CRC15_POL             :     std_logic_vector(15 downto 0) := x"C599";
        
        -- CRC 17 polynomial
        G_CRC17_POL             :     std_logic_vector(19 downto 0) := x"3685B";
        
        -- CRC 15 polynomial
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        G_CRC21_POL             :     std_logic_vector(23 downto 0) := x"302899";
        
        -- Support traffic counters
        G_SUP_TRAFFIC_CTRS      :     boolean := true
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    );
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    port(
        ------------------------------------------------------------------------
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        -- Clock and Asynchronous reset
        ------------------------------------------------------------------------
        -- System clock
        clk_sys                :in   std_logic;
        
        -- Asynchronous reset
        res_n                  :in   std_logic;
        
        ------------------------------------------------------------------------    
        -- Memory registers interface
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        ------------------------------------------------------------------------
        -- Driving bus
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        drv_bus                :in   std_logic_vector(1023 downto 0);
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        -- Status bus
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        stat_bus               :out  std_logic_vector(511 downto 0);
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        ------------------------------------------------------------------------
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        -- Tx Arbitrator and TXT Buffers interface
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        ------------------------------------------------------------------------
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        -- TX Data word
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        tran_word              :in   std_logic_vector(31 downto 0);
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        -- TX Data length code
        tran_dlc               :in   std_logic_vector(3 downto 0);
        
        -- TX Remote transmission request flag
        tran_is_rtr            :in   std_logic;
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        -- TX Identifier type (0-Basic, 1-Extended)
        tran_ident_type        :in   std_logic;
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        -- TX Frame type (0-CAN 2.0, 1-CAN FD)
        tran_frame_type        :in   std_logic;
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        -- TX Bit Rate Shift
        tran_brs               :in   std_logic;
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        -- TX Identifier
        tran_identifier        :in   std_logic_vector(28 downto 0);
        
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        -- Frame in TXT Buffer is valid any can be transmitted.
        tran_frame_valid       :in   std_logic; 
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        -- HW Commands for TX Arbitrator and TXT Buffers
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        txtb_hw_cmd            :out  t_txtb_hw_cmd;
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        -- Selected TXT Buffer index changed
        txtb_changed           :in   std_logic;
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        -- Pointer to TXT buffer memory
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        txtb_ptr               :out  natural range 0 to 19;
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        -- Transition to bus off has occurred
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        is_bus_off             :out  std_logic;
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        ------------------------------------------------------------------------
        -- Recieve Buffer and Message Filter Interface
        ------------------------------------------------------------------------
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        -- RX CAN Identifier
        rec_ident              :out  std_logic_vector(28 downto 0);
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        -- RX Data length code
        rec_dlc                :out  std_logic_vector(3 downto 0);
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        -- RX Recieved identifier type (0-BASE Format, 1-Extended Format);
        rec_ident_type         :out  std_logic;
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        -- RX frame type (0-CAN 2.0, 1- CAN FD) 
        rec_frame_type         :out  std_logic;
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        -- RX Remote transmission request Flag
        rec_is_rtr             :out  std_logic;
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        -- RX Bit Rate Shift bit
        rec_brs                :out  std_logic;
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        -- RX Error state indicator
        rec_esi      	       :out  std_logic;
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        -- RX Frame received succesfully, can be commited to RX Buffer.
        rec_valid              :out  std_logic; 
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        -- Metadata are received OK, and can be stored in RX Buffer.
        store_metadata         :out  std_logic;
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        -- Store data word to RX Buffer. 
        store_data             :out  std_logic;
        
        -- Data words to be stored to RX Buffer.
        store_data_word        :out  std_logic_vector(31 downto 0);
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        -- Abort storing of frame in RX Buffer. Revert to last frame.
        rec_abort              :out  std_logic;
        
        -- Pulse in Start of Frame
        sof_pulse              :out  std_logic;
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        ------------------------------------------------------------------------
        -- Interrupt Manager Interface 
        ------------------------------------------------------------------------
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        -- Arbitration was lost
        arbitration_lost       :out  std_logic;
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        -- Frame stored in CAN Core was sucessfully transmitted
        tran_valid             :out  std_logic; 
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        -- Bit Rate Was Shifted
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        br_shifted             :out  std_logic;
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        -- Error is detected (Error frame will be transmitted)
        err_detected           :out  std_logic;
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        -- Fault confinement state changed
        fcs_changed            :out  std_logic;
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        -- Error warning limit reached
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        err_warning_limit      :out  std_logic;
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        -- Overload frame is being transmitted
        is_overload            :out  std_logic;
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        ------------------------------------------------------------------------
        -- Prescaler interface 
        ------------------------------------------------------------------------
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        -- RX Triggers (in Sample Point)
        rx_triggers   :in   std_logic_vector(G_SAMPLE_TRIGGER_COUNT - 1 downto 0);
        
        -- TX Trigger
        tx_trigger    :in   std_logic;
        
        -- Synchronisation control (No synchronisation, Hard Synchronisation,
        -- Resynchronisation
        sync_control  :out  std_logic_vector(1 downto 0);
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        -- No positive resynchronisation 
        no_pos_resync :out  std_logic;
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        -- Sample control (Nominal, Data, Secondary)
        sp_control    :out  std_logic_vector(1 downto 0); 

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        -- Enable Nominal Bit time counters.
        nbt_ctrs_en   :out  std_logic;
        
        -- Enable Data Bit time counters.
        dbt_ctrs_en   :out  std_logic;
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        ------------------------------------------------------------------------
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        -- CAN Bus serial data stream
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        ------------------------------------------------------------------------
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        -- RX Data from CAN Bus
        rx_data_wbs         :in   std_logic; 
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        -- TX Data to CAN Bus
        tx_data_wbs         :out  std_logic; 
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        ------------------------------------------------------------------------
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        -- Others
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        ------------------------------------------------------------------------
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        timestamp           :in   std_logic_vector(63 downto 0);
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        -- Secondary sample point reset
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        ssp_reset           :out  std_logic; 
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        -- Enable measurement of Transmitter delay
        tran_delay_meas     :out  std_logic;
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        -- Bit Error detected 
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        bit_err             :in   std_logic;
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        -- Secondary sample signal 
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        sample_sec          :in   std_logic;
        
        -- Reset Bit time measurement counter
        btmc_reset          :out   std_logic;
    
        -- Start Measurement of data bit time (in TX Trigger)
        dbt_measure_start   :out  std_logic;
    
        -- First SSP generated (in ESI bit)
        gen_first_ssp       :out  std_logic
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    );
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end entity;

architecture rtl of can_core is
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    ----------------------------------------------------------------------------
    -- Driving bus aliases
    ----------------------------------------------------------------------------
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    signal drv_clr_rx_ctr          :     std_logic;
    signal drv_clr_tx_ctr          :     std_logic;
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    signal drv_bus_mon_ena         :     std_logic;
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    signal drv_ena                 :     std_logic;
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    ----------------------------------------------------------------------------
    ----------------------------------------------------------------------------
    -- Internal signals
    ----------------------------------------------------------------------------
    ----------------------------------------------------------------------------

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    -- TXT Buffer control
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    signal txtb_hw_cmd_i             :   t_txtb_hw_cmd;
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    -- Received frame
    signal rec_ident_i              :   std_logic_vector(28 downto 0);
    signal rec_dlc_i                :   std_logic_vector(3 downto 0);
    signal rec_ident_type_i         :   std_logic;
    signal rec_frame_type_i         :   std_logic;
    signal rec_is_rtr_i             :   std_logic;
    signal rec_brs_i                :   std_logic;
    signal rec_esi_i                :   std_logic;
    
    -- Arbitration lost capture
    signal alc                      :   std_logic_vector(7 downto 0);
    
    -- Error code capture
    signal erc_capture              :   std_logic_vector(7 downto 0);
    
    -- Operation control interface
    signal is_transmitter           :   std_logic;
    signal is_receiver              :   std_logic;
    signal is_idle                  :   std_logic;
    signal arbitration_lost_i       :   std_logic;
    signal set_transmitter          :   std_logic;
    signal set_receiver             :   std_logic;
    signal set_idle                 :   std_logic;
    
    -- Fault confinement Interface
    signal is_err_active           :    std_logic;
    signal is_err_passive          :    std_logic;
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    signal is_bus_off_i            :    std_logic;
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    signal err_detected_i          :    std_logic;
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    signal primary_err             :    std_logic;
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    signal act_err_ovr_flag        :    std_logic;
    signal err_delim_late          :    std_logic;
    signal set_err_active          :    std_logic;
    signal err_ctrs_unchanged      :    std_logic;

    -- Bit Stuffing Interface
    signal stuff_enable            :    std_logic;
    signal destuff_enable          :    std_logic;
    signal fixed_stuff             :    std_logic;
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    signal tx_frame_no_sof         :    std_logic;
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    signal stuff_length            :    std_logic_vector(2 downto 0);
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    signal dst_ctr                 :    std_logic_vector(2 downto 0);
    signal bst_ctr                 :    std_logic_vector(2 downto 0);
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    signal stuff_err               :    std_logic;
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    -- CRC Interface
    signal crc_enable              :    std_logic;
    signal crc_spec_enable         :    std_logic;
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    signal crc_calc_from_rx        :    std_logic;
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    signal crc_15                  :    std_logic_vector(14 downto 0);
    signal crc_17                  :    std_logic_vector(16 downto 0);
    signal crc_21                  :    std_logic_vector(20 downto 0);

    -- Protocol control - control outputs
    signal sp_control_i            :    std_logic_vector(1 downto 0);
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    signal sp_control_q            :    std_logic_vector(1 downto 0);
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    signal sync_control_i          :    std_logic_vector(1 downto 0); 
    signal ssp_reset_i             :    std_logic;
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    signal tran_delay_meas_i       :    std_logic;
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    signal tran_valid_i            :    std_logic;
    signal rec_valid_i             :    std_logic;
    signal ack_received_i          :    std_logic;
    signal br_shifted_i            :    std_logic;
    
    -- Fault confinement status signals
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    signal fcs_changed_i           :    std_logic;
    signal err_warning_limit_i     :    std_logic;
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    signal tx_err_ctr              :    std_logic_vector(8 downto 0);
    signal rx_err_ctr              :    std_logic_vector(8 downto 0);
    signal norm_err_ctr            :    std_logic_vector(15 downto 0);
    signal data_err_ctr            :    std_logic_vector(15 downto 0);
    
    -- Protocol control triggers
    signal pc_tx_trigger           :    std_logic;
    signal pc_rx_trigger           :    std_logic;
    
    -- Protocol control data inputs/outputs
    signal pc_tx_data_nbs          :    std_logic;
    signal pc_rx_data_nbs          :    std_logic;
    
    -- CRC Data inputs
    signal crc_data_tx_wbs         :    std_logic;
    signal crc_data_tx_nbs         :    std_logic;
    signal crc_data_rx_wbs         :    std_logic;
    signal crc_data_rx_nbs         :    std_logic;
    
    -- CRC Trigger inputs
    signal crc_trig_tx_wbs         :    std_logic;
    signal crc_trig_tx_nbs         :    std_logic;
    signal crc_trig_rx_wbs         :    std_logic;
    signal crc_trig_rx_nbs         :    std_logic;
    
    -- Bit stuffing signals
    signal bst_data_in             :    std_logic;
    signal bst_data_out            :    std_logic;
    signal bst_trigger             :    std_logic;
    signal data_halt               :    std_logic;
    
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    -- Bit destuffing signals
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    signal bds_data_in             :    std_logic;
    signal bds_data_out            :    std_logic;
    signal bds_trigger             :    std_logic;
    signal destuffed               :    std_logic;
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    -- Bus traffic counters
    signal tx_ctr                  :    std_logic_vector(31 downto 0);
    signal rx_ctr                  :    std_logic_vector(31 downto 0);
    
    signal tx_data_wbs_i           :    std_logic;
    
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    -- Looped back data for bus monitoring mode
    signal lpb_dominant            :    std_logic;
    
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    -- Error indication
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    signal form_err                :    std_logic;
    signal ack_err                 :    std_logic;
    signal crc_err                 :    std_logic;
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    -- Protocol control debug  information
    signal is_arbitration          :     std_logic;
    signal is_control              :     std_logic;
    signal is_data                 :     std_logic;
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    signal is_stuff_count          :     std_logic;
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    signal is_crc                  :     std_logic;
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    signal is_crc_delim            :     std_logic;
    signal is_ack_field            :     std_logic;
    signal is_ack_delim            :     std_logic;
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    signal is_eof                  :     std_logic;
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    signal is_err_frm              :     std_logic;
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    signal is_intermission         :     std_logic;
    signal is_suspend              :     std_logic;
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    signal is_overload_i           :     std_logic;
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    signal is_sof                  :     std_logic;
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    signal sof_pulse_i             :     std_logic;
    
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    signal load_init_vect          :     std_logic;
    
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    signal retr_ctr_i              :     std_logic_vector(G_RETR_LIM_CTR_WIDTH - 1 downto 0);
    
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begin
  
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    ----------------------------------------------------------------------------
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    -- Driving bus aliases
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    ----------------------------------------------------------------------------
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    drv_clr_rx_ctr        <=  drv_bus(DRV_CLR_RX_CTR_INDEX);
    drv_clr_tx_ctr        <=  drv_bus(DRV_CLR_TX_CTR_INDEX);
    drv_bus_mon_ena       <=  drv_bus(DRV_BUS_MON_ENA_INDEX);
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    drv_ena               <=  drv_bus(DRV_ENA_INDEX);
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    ----------------------------------------------------------------------------
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    -- Protocol control
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    ----------------------------------------------------------------------------
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    protocol_control_inst : protocol_control
    generic map(
        G_RESET_POLARITY        => G_RESET_POLARITY,
        G_CTRL_CTR_WIDTH        => G_CTRL_CTR_WIDTH,
        G_RETR_LIM_CTR_WIDTH    => G_RETR_LIM_CTR_WIDTH,
        G_ERR_VALID_PIPELINE    => G_ERR_VALID_PIPELINE
    )
    port map(
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        clk_sys                 => clk_sys,             -- IN
        res_n                   => res_n,               -- IN
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        -- Memory registers interface
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        drv_bus                 => drv_bus,             -- IN
        alc                     => alc,                 -- OUT
        erc_capture             => erc_capture,         -- OUT
        is_arbitration          => is_arbitration,      -- OUT
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        is_control              => is_control,          -- OUT
        is_data                 => is_data,             -- OUT
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        is_stuff_count          => is_stuff_count,      -- OUT
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        is_crc                  => is_crc,              -- OUT
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        is_crc_delim            => is_crc_delim,        -- OUT
        is_ack_field            => is_ack_field,        -- OUT
        is_ack_delim            => is_ack_delim,        -- OUT
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        is_eof                  => is_eof,              -- OUT
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        is_intermission         => is_intermission,     -- OUT
        is_suspend              => is_suspend,          -- OUT
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        is_err_frm              => is_err_frm,          -- OUT
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        is_overload             => is_overload_i,       -- OUT
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        is_sof                  => is_sof,              -- OUT
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        -- TXT Buffers interface
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        tran_word               => tran_word,           -- IN
        tran_dlc                => tran_dlc,            -- IN
        tran_is_rtr             => tran_is_rtr,         -- IN
        tran_ident_type         => tran_ident_type,     -- IN
        tran_frame_type         => tran_frame_type,     -- IN
        tran_brs                => tran_brs,            -- IN
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        tran_identifier         => tran_identifier,     -- IN
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        tran_frame_valid        => tran_frame_valid,    -- IN
        txtb_hw_cmd             => txtb_hw_cmd_i,       -- IN
        txtb_ptr                => txtb_ptr,            -- OUT
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        txtb_changed            => txtb_changed,        -- OUT
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        -- RX Buffer interface
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        rec_ident               => rec_ident_i,         -- OUT
        rec_dlc                 => rec_dlc_i,           -- OUT
        rec_is_rtr              => rec_is_rtr_i,        -- OUT
        rec_ident_type          => rec_ident_type_i,    -- OUT
        rec_frame_type          => rec_frame_type_i,    -- OUT
        rec_brs                 => rec_brs_i,           -- OUT
        rec_esi                 => rec_esi_i,           -- OUT
        store_metadata          => store_metadata,      -- OUT
        rec_abort               => rec_abort,           -- OUT
        store_data              => store_data,          -- OUT
        store_data_word         => store_data_word,     -- OUT
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        sof_pulse               => sof_pulse_i,         -- OUT
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        -- Operation control FSM Interface
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        is_transmitter          => is_transmitter,      -- IN
        is_receiver             => is_receiver,         -- IN
        is_idle                 => is_idle,             -- IN
        arbitration_lost        => arbitration_lost_i,  -- OUT
        set_transmitter         => set_transmitter,     -- OUT
        set_receiver            => set_receiver,        -- OUT
        set_idle                => set_idle,            -- OUT
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        -- Fault confinement Interface
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        is_err_active           => is_err_active,       -- IN
        is_err_passive          => is_err_passive,      -- IN
        is_bus_off              => is_bus_off_i,        -- IN
        err_detected            => err_detected_i,      -- OUT
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        primary_err             => primary_err,         -- OUT
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        act_err_ovr_flag        => act_err_ovr_flag,    -- OUT
        err_delim_late          => err_delim_late,      -- OUT
        set_err_active          => set_err_active,      -- OUT
        err_ctrs_unchanged      => err_ctrs_unchanged,  -- OUT
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        -- TX and RX Trigger signals to Sample and Transmitt Data
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        tx_trigger              => pc_tx_trigger,       -- IN
        rx_trigger              => pc_rx_trigger,       -- IN
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        -- CAN Bus serial data stream
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        tx_data_nbs             => pc_tx_data_nbs,      -- OUT
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        tx_data_wbs             => tx_data_wbs_i,
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        rx_data_nbs             => pc_rx_data_nbs,      -- IN
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        -- Bit Stuffing Interface
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        stuff_enable            => stuff_enable,        -- OUT
        destuff_enable          => destuff_enable,      -- OUT
        fixed_stuff             => fixed_stuff,         -- OUT
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        tx_frame_no_sof         => tx_frame_no_sof,     -- OUT
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        stuff_length            => stuff_length,        -- OUT
        dst_ctr                 => dst_ctr,             -- IN
        bst_ctr                 => bst_ctr,             -- IN
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        stuff_err               => stuff_err,           -- IN
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        -- Bus Sampling Interface
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        bit_err                 => bit_err,             -- IN
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        btmc_reset              => btmc_reset,          -- OUT
        dbt_measure_start       => dbt_measure_start,   -- OUT
        gen_first_ssp           => gen_first_ssp,       -- OUT
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        -- CRC Interface
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        crc_enable              => crc_enable,          -- OUT
        crc_spec_enable         => crc_spec_enable,     -- OUT
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        crc_calc_from_rx        => crc_calc_from_rx,    -- OUT
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        load_init_vect          => load_init_vect,      -- OUT
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        crc_15                  => crc_15,              -- IN
        crc_17                  => crc_17,              -- IN
        crc_21                  => crc_21,              -- IN
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        -- Control signals
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        sp_control              => sp_control_i,        -- OUT
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        sp_control_q            => sp_control_q,        -- OUT
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        nbt_ctrs_en             => nbt_ctrs_en,         -- OUT
        dbt_ctrs_en             => dbt_ctrs_en,         -- OUT
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        sync_control            => sync_control_i,      -- OUT
        no_pos_resync           => no_pos_resync,       -- OUT
        ssp_reset               => ssp_reset_i,         -- OUT
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        tran_delay_meas         => tran_delay_meas_i,   -- OUT
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        tran_valid              => tran_valid_i,        -- OUT
        rec_valid               => rec_valid_i,         -- OUT
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        -- Status signals
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        ack_received            => ack_received_i,      -- OUT
        br_shifted              => br_shifted_i,        -- OUT
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        form_err                => form_err,            -- OUT
        ack_err                 => ack_err,             -- OUT
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        crc_err                 => crc_err,             -- OUT
        retr_ctr                => retr_ctr_i           -- OUT
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    );
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    ---------------------------------------------------------------------------
    -- Operation control FSM
    ---------------------------------------------------------------------------
    operation_control_inst : operation_control
    generic map(
        G_RESET_POLARITY     => G_RESET_POLARITY    
    )
    port map(
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        clk_sys              => clk_sys,                -- IN
        res_n                => res_n,                  -- IN
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        -- Memory registers Interface
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        drv_bus              => drv_bus,                -- IN
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        -- Prescaler Interface
        rx_trigger           => pc_rx_trigger,          -- IN
        
        -- Fault confinement Interface
        is_bus_off           => is_bus_off_i,           -- IN
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        -- Protocol Control Interface
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        arbitration_lost     => arbitration_lost_i,     -- IN
        set_transmitter      => set_transmitter,        -- IN
        set_receiver         => set_receiver,           -- IN
        set_idle             => set_idle,               -- IN
        is_transmitter       => is_transmitter,         -- OUT
        is_receiver          => is_receiver,            -- OUT
        is_idle              => is_idle                 -- OUT
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    );
    
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    ---------------------------------------------------------------------------
    -- Fault confinement
    ---------------------------------------------------------------------------
    fault_confinement_inst : fault_confinement
    generic map(
        G_RESET_POLARITY     => G_RESET_POLARITY
    )
    port map(
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        clk_sys                 => clk_sys,                 -- IN
        res_n                   => res_n,                   -- IN
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        -- Memory registers interface
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        drv_bus                 => drv_bus,                 -- IN
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        -- Error signalling for interrupts
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        fcs_changed             => fcs_changed_i,           -- OUT
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        err_warning_limit       => err_warning_limit_i,     -- OUT
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        -- Operation control Interface
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        is_transmitter          => is_transmitter,          -- IN
        is_receiver             => is_receiver,             -- IN
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        -- Protocol control Interface
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        sp_control              => sp_control_i,            -- IN
        set_err_active          => set_err_active,          -- IN
        err_detected            => err_detected_i,          -- IN
        err_ctrs_unchanged      => err_ctrs_unchanged,      -- IN
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        primary_err             => primary_err,             -- IN
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        act_err_ovr_flag        => act_err_ovr_flag,        -- IN
        err_delim_late          => err_delim_late,          -- IN
        tran_valid              => tran_valid_i,            -- IN
        rec_valid               => rec_valid_i,             -- IN
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        -- Fault confinement State indication
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        is_err_active           => is_err_active,           -- OUT
        is_err_passive          => is_err_passive,          -- OUT
        is_bus_off              => is_bus_off_i,            -- OUT
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        -- Error counters
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        tx_err_ctr              => tx_err_ctr,              -- OUT
        rx_err_ctr              => rx_err_ctr,              -- OUT
        norm_err_ctr            => norm_err_ctr,            -- OUT
        data_err_ctr            => data_err_ctr             -- OUT
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    );
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    ---------------------------------------------------------------------------
    -- CAN CRC
    ---------------------------------------------------------------------------
    can_crc_inst : can_crc
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    generic map(
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        G_RESET_POLARITY    => G_RESET_POLARITY,
        G_CRC15_POL         => G_CRC15_POL,
        G_CRC17_POL         => G_CRC17_POL,
        G_CRC21_POL         => G_CRC21_POL
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    )
    port map(
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        clk_sys          => clk_sys,                    -- IN
        res_n            => res_n,                      -- IN
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        -- Memory registers interface
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        drv_bus          => drv_bus,                    -- IN
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        -- Data inputs for CRC calculation
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        data_tx_wbs      => crc_data_tx_wbs,            -- IN
        data_tx_nbs      => crc_data_tx_nbs,            -- IN
        data_rx_wbs      => crc_data_rx_wbs,            -- IN
        data_rx_nbs      => crc_data_rx_nbs,            -- IN
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        -- Trigger signals to process the data on each CRC input.
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        trig_tx_wbs      => crc_trig_tx_wbs,            -- IN
        trig_tx_nbs      => crc_trig_tx_nbs,            -- IN
        trig_rx_wbs      => crc_trig_rx_wbs,            -- IN
        trig_rx_nbs      => crc_trig_rx_nbs,            -- IN
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        -- Control signals
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        crc_enable       => crc_enable,                 -- IN
        crc_spec_enable  => crc_spec_enable,            -- IN
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        crc_calc_from_rx => crc_calc_from_rx,           -- IN
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        is_receiver      => is_receiver,                -- IN
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        load_init_vect   => load_init_vect,             -- IN
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        -- CRC Outputs
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        crc_15           => crc_15,                     -- OUT
        crc_17           => crc_17,                     -- OUT
        crc_21           => crc_21                      -- OUT
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    );
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    ---------------------------------------------------------------------------
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    -- Bit Stuffing
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    ---------------------------------------------------------------------------
    bit_stuffing_inst : bit_stuffing
    generic map(
        G_RESET_POLARITY    => G_RESET_POLARITY
    )
    port map(
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        clk_sys             => clk_sys,                 -- IN
        res_n               => res_n,                   -- IN
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        -- Data-path
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        data_in             => bst_data_in,             -- IN
        data_out            => bst_data_out,            -- OUT
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        -- Control signals
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        bst_trigger         => bst_trigger,             -- IN
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        stuff_enable        => stuff_enable,            -- IN
        fixed_stuff         => fixed_stuff,             -- IN
        stuff_length        => stuff_length,            -- IN
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        tx_frame_no_sof     => tx_frame_no_sof,         -- IN
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        -- Status signals
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        bst_ctr             => bst_ctr,                 -- OUT
        data_halt           => data_halt                -- OUT
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    );
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    ---------------------------------------------------------------------------
    -- Bit Destuffing
    ---------------------------------------------------------------------------
    bit_destuffing_inst : bit_destuffing
    generic map(
        G_RESET_POLARITY    => G_RESET_POLARITY
    )
    port map(
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        clk_sys             => clk_sys,                 -- IN
        res_n               => res_n,                   -- IN
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        -- Data-path
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        data_in             => bds_data_in,             -- IN
        data_out            => bds_data_out,            -- OUT
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        -- Control signals
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        bds_trigger         => bds_trigger,             -- IN
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        destuff_enable      => destuff_enable,          -- IN
        fixed_stuff         => fixed_stuff,             -- IN
        destuff_length      => stuff_length,            -- IN
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        -- Status Outpus
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        stuff_err           => stuff_err,               -- OUT
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        destuffed           => destuffed,               -- OUT
        dst_ctr             => dst_ctr                  -- OUT
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    );
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    ---------------------------------------------------------------------------
    -- Bus traffic counters
    ---------------------------------------------------------------------------
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    bus_traffic_ctrs_gen : if (G_SUP_TRAFFIC_CTRS = true) generate
        bus_traffic_counters_inst : bus_traffic_counters
        generic map(
            G_RESET_POLARITY    => G_RESET_POLARITY
        )
        port map(
            clk_sys             => clk_sys,                 -- IN
            res_n               => res_n,                   -- IN
    
            -- Control signals
            clear_rx_ctr        => drv_clr_rx_ctr,          -- IN
            clear_tx_ctr        => drv_clr_tx_ctr,          -- IN
            inc_tx_ctr          => tran_valid_i,            -- IN
            inc_rx_ctr          => rec_valid_i,             -- IN
    
            -- Counter outputs
            tx_ctr              => tx_ctr,                  -- OUT
            rx_ctr              => rx_ctr                   -- OUT
        );
    end generate bus_traffic_ctrs_gen;
    
    no_bus_traffic_ctrs_gen : if (G_SUP_TRAFFIC_CTRS = false) generate
        tx_ctr <= (OTHERS => '0');
        rx_ctr <= (OTHERS => '0');
    end generate;
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    ---------------------------------------------------------------------------
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    -- Trigger multiplexor    
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    ---------------------------------------------------------------------------
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    trigger_mux_inst : trigger_mux
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    generic map(
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        G_RESET_POLARITY        => G_RESET_POLARITY,
        G_SAMPLE_TRIGGER_COUNT  => G_SAMPLE_TRIGGER_COUNT
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    )
    port map(
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        -- Clock and Asynchronous reset
        clk_sys                => clk_sys,
        res_n                  => res_n,
        
        -- Input triggers
        rx_triggers            => rx_triggers,
        tx_trigger             => tx_trigger,
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        -- Control signals
        data_halt              => data_halt,
        destuffed              => destuffed,
        fixed_stuff            => fixed_stuff,
        bds_data_in            => bds_data_in,

        -- Output triggers
        pc_tx_trigger          => pc_tx_trigger,
        pc_rx_trigger          => pc_rx_trigger,
        bst_trigger            => bst_trigger,
        bds_trigger            => bds_trigger,
        crc_trig_rx_nbs        => crc_trig_rx_nbs,
        crc_trig_tx_nbs        => crc_trig_tx_nbs,
        crc_trig_rx_wbs        => crc_trig_rx_wbs,
        crc_trig_tx_wbs        => crc_trig_tx_wbs,
        
        -- Status signals
        crc_data_rx_wbs        => crc_data_rx_wbs
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    );
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    ---------------------------------------------------------------------------
    ---------------------------------------------------------------------------
    -- Datapath connection    
    ---------------------------------------------------------------------------
    ---------------------------------------------------------------------------
  
    ---------------------------------------------------------------------------
    -- Protocol control datapath connection:
    --  1. RX Data - Output of bit destuffing.
    --  2. TX Data - Input to bit stuffing.
    ---------------------------------------------------------------------------
    pc_rx_data_nbs <= bds_data_out;
    bst_data_in <= pc_tx_data_nbs;
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    ---------------------------------------------------------------------------
    -- CRC 15 (No bit stuffing) data inputs:
    --  1. TX Data from Protocol control.
    --  2. RX Data after bit destuffing.
    ---------------------------------------------------------------------------
    crc_data_tx_nbs <= pc_tx_data_nbs;
    crc_data_rx_nbs <= bds_data_out;
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    ---------------------------------------------------------------------------
    -- CRC 17,21 (With bit stuffing) data inputs:
    --  1. TX Data after Bit stuffing.
    --  2. RX Data before Bit destuffing.
    ---------------------------------------------------------------------------
    crc_data_tx_wbs <= bst_data_out;
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    lpb_dominant <= rx_data_wbs and bst_data_out;
    
    ---------------------------------------------------------------------------
    -- Bit Stuffing data input:
    --  1. Bit Destuffing output for secondary sampling. This-way core will
    --     automatically receive what it transmitts without loop over
    --     Transceiver. Bit Error is detected by Bus sampling properly.
    --  2. Looped back dominant Bit for Bus monitoring Mode.
    --  3. Regular RX Data
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    ---------------------------------------------------------------------------
877
    bds_data_in <= bst_data_out when (sp_control_q = SECONDARY_SAMPLE) else
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                   lpb_dominant when (drv_bus_mon_ena = '1') else
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                    rx_data_wbs;
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    ---------------------------------------------------------------------------
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    -- In Bus monitoring mode or when core is disabled, transmitted data to the
    -- bus are only recessive. Otherwise transmitted data are stuffed data!
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    ---------------------------------------------------------------------------
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    tx_data_wbs_i <= RECESSIVE when (drv_ena = CTU_CAN_DISABLED) else
                     RECESSIVE when (drv_bus_mon_ena = '1') else
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                     bst_data_out;
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890 891 892
    ----------------------------------------------------------------------------
    -- STATUS Bus Implementation
    ----------------------------------------------------------------------------
893
    stat_bus(511 downto 385) <= (OTHERS => '0');
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    stat_bus(299 downto 297) <= (OTHERS => '0');
    stat_bus(98 downto 90)   <= (OTHERS => '0');
    stat_bus(60 downto 32)   <= (OTHERS => '0');
    stat_bus(113)            <= '0';
    stat_bus(115)            <= '0';
    stat_bus(183)            <= '0';
    stat_bus(120 downto 118) <= (OTHERS => '0');
    stat_bus(178 downto 158) <= (OTHERS => '0');

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    stat_bus(27)             <= '0';

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    stat_bus(STAT_BR_SHIFTED) <=
        br_shifted_i;

    stat_bus(STAT_ERC_ERR_TYPE_HIGH downto STAT_ERC_ERR_POS_LOW) <=
        erc_capture;

    stat_bus(STAT_IS_TRANSMITTER_INDEX) <=
        is_transmitter;

    stat_bus(STAT_IS_RECEIVER_INDEX) <=
        is_receiver;
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    stat_bus(STAT_SOF_PULSE_INDEX) <=
        sof_pulse_i;
    
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    stat_bus(STAT_PC_IS_ARBITRATION_INDEX) <=
        is_arbitration;
               
    stat_bus(STAT_PC_IS_CONTROL_INDEX) <=
        is_control;
    
    stat_bus(STAT_PC_IS_DATA_INDEX) <=
        is_data;
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    stat_bus(STAT_PC_IS_STUFF_COUNT_INDEX) <=
        is_stuff_count;
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    stat_bus(STAT_PC_IS_CRC_INDEX) <=
        is_crc;
    
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    stat_bus(STAT_PC_IS_CRC_DELIM_INDEX) <=
        is_crc_delim;
    
    stat_bus(STAT_PC_IS_ACK_FIELD_INDEX) <=
        is_ack_field;
        
    stat_bus(STAT_PC_IS_ACK_DELIM_INDEX) <=
        is_ack_delim;
    
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    stat_bus(STAT_PC_IS_EOF_INDEX) <=
        is_eof;
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    stat_bus(STAT_PC_IS_INTERMISSION_INDEX) <=
        is_intermission;
    
    stat_bus(STAT_PC_IS_SUSPEND_INDEX) <=
        is_suspend;
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953 954
    stat_bus(STAT_PC_IS_ERR_INDEX) <=
        is_err_frm;
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    stat_bus(STAT_PC_IS_OVERLOAD_INDEX) <=
        is_overload_i;

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    stat_bus(STAT_PC_IS_SOF) <=
        is_sof;

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    stat_bus(STAT_ARB_LOST_INDEX) <=
        arbitration_lost_i;
        
    stat_bus(STAT_SET_TRANSC_INDEX) <= 
        set_transmitter;
        
    stat_bus(STAT_SET_REC_INDEX) <=
        set_receiver;
        
    stat_bus(STAT_IS_IDLE_INDEX) <=
        is_idle;
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    stat_bus(STAT_SP_CONTROL_HIGH downto STAT_SP_CONTROL_LOW) <=
        sp_control_i;
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    stat_bus(STAT_SSP_RESET_INDEX) <=
        ssp_reset_i;
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    stat_bus(STAT_TRAN_DELAY_MEAS_INDEX) <=
        tran_delay_meas_i;
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    stat_bus(STAT_SYNC_CONTROL_HIGH downto STAT_SYNC_CONTROL_LOW) <= 
        sync_control_i;
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    stat_bus(STAT_DATA_TX_INDEX) <=
        tx_data_wbs_i;
        
    stat_bus(STAT_DATA_RX_INDEX) <=
        rx_data_wbs;
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    stat_bus(STAT_BS_ENABLE_INDEX) <=
        stuff_enable;
        
    stat_bus(STAT_FIXED_STUFF_INDEX) <=
        fixed_stuff;
        
    stat_bus(STAT_DATA_HALT_INDEX) <=
        data_halt;
        
    stat_bus(STAT_BS_LENGTH_HIGH downto STAT_BS_LENGTH_LOW) <=
        stuff_length;
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    stat_bus(STAT_STUFF_ERR_INDEX) <=
        stuff_err;
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    stat_bus(STAT_DESTUFFED_INDEX) <=
        destuffed;
        
    stat_bus(STAT_BDS_ENA_INDEX) <=
        destuff_enable;
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    stat_bus(STAT_FIXED_DESTUFF_INDEX) <=
        fixed_stuff;
        
    stat_bus(STAT_BDS_LENGTH_HIGH downto STAT_BDS_LENGTH_LOW) <=
        stuff_length;
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    stat_bus(STAT_TRAN_DLC_HIGH downto STAT_TRAN_DLC_LOW) <=
        tran_dlc;
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    stat_bus(STAT_TRAN_IS_RTR_INDEX) <=
        tran_is_rtr;
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    stat_bus(STAT_TRAN_IDENT_TYPE_INDEX) <=
        tran_ident_type;
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    stat_bus(STAT_TRAN_FRAME_TYPE_INDEX) <=
        tran_frame_type;
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    stat_bus(STAT_TRAN_DATA_ACK_INDEX) <=
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        txtb_hw_cmd_i.lock;