bus_sampling.vhd 18.3 KB
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--------------------------------------------------------------------------------
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-- 
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-- CTU CAN FD IP Core
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-- Copyright (C) 2015-2018
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-- 
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-- Authors:
--     Ondrej Ille <ondrej.ille@gmail.com>
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--     Martin Jerabek <martin.jerabek01@gmail.com>
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-- 
-- Project advisors: 
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-- 	Jiri Novak <jnovak@fel.cvut.cz>
-- 	Pavel Pisa <pisa@cmp.felk.cvut.cz>
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-- 
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-- Department of Measurement         (http://meas.fel.cvut.cz/)
-- Faculty of Electrical Engineering (http://www.fel.cvut.cz)
-- Czech Technical University        (http://www.cvut.cz/)
-- 
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-- Permission is hereby granted, free of charge, to any person obtaining a copy
-- of this VHDL component and associated documentation files (the "Component"),
-- to deal in the Component without restriction, including without limitation
-- the rights to use, copy, modify, merge, publish, distribute, sublicense,
-- and/or sell copies of the Component, and to permit persons to whom the
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-- Component is furnished to do so, subject to the following conditions:
-- 
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-- The above copyright notice and this permission notice shall be included in
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-- all copies or substantial portions of the Component.
-- 
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-- THE COMPONENT IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-- IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-- FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
-- AUTHORS OR COPYRIGHTHOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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-- LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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-- FROM, OUT OF OR IN CONNECTION WITH THE COMPONENT OR THE USE OR OTHER DEALINGS
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-- IN THE COMPONENT.
-- 
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-- The CAN protocol is developed by Robert Bosch GmbH and protected by patents.
-- Anybody who wants to implement this IP core on silicon has to obtain a CAN
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-- protocol license from Bosch.
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-- 
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--------------------------------------------------------------------------------

--------------------------------------------------------------------------------
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-- Module:
--  Bus sampling
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--
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-- Sub-modules:
--  1. CAN RX synchronisation chain
--  2. Transceiver Delay measurement
--  3. Data edge detector
--  4. Secondary sampling point shift register.
--  5. TX Data cache.
--  6. Bit Error detector.
--  7. Sample multiplexor.
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--------------------------------------------------------------------------------
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Library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.ALL;

Library work;
use work.id_transfer.all;
use work.can_constants.all;
use work.can_components.all;
use work.can_types.all;
use work.cmn_lib.all;
use work.drv_stat_pkg.all;
use work.reduce_lib.all;

use work.CAN_FD_register_map.all;
use work.CAN_FD_frame_format.all;
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entity bus_sampling is 
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    generic(        
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        -- Reset polarity
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        G_RESET_POLARITY        :     std_logic := '0';
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        -- Secondary sampling point Shift registers length
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        G_SSP_DELAY_SAT_VAL     :     natural := 255;
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        -- Depth of FIFO Cache for TX Data
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        G_TX_CACHE_DEPTH        :     natural := 8;
        
        -- Width (number of bits) in transceiver delay measurement counter
        G_TRV_CTR_WIDTH         :     natural := 7;
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        -- Width of SSP position
        G_SSP_POS_WIDTH          :    natural := 8;

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        -- Optional usage of saturated value of ssp_delay 
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        G_USE_SSP_SATURATION    :     boolean := true;
        
        -- Width of SSP generator counters (BTMC, SSPC)
        G_SSP_CTRS_WIDTH        :      natural := 14
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    );  
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    port(
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        ------------------------------------------------------------------------
        -- Clock and Async reset
        ------------------------------------------------------------------------
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        -- System clock
        clk_sys              :in   std_logic;
        
        -- Asynchronous reset
        res_n                :in   std_logic;
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        ------------------------------------------------------------------------
        --  Physical layer interface
        ------------------------------------------------------------------------
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        -- CAN serial stream output
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        can_rx               :in   std_logic;
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        -- CAN serial stream input
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        can_tx               :out  std_logic;
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        ------------------------------------------------------------------------
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        -- Memory registers interface
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        ------------------------------------------------------------------------
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        -- Driving bus
        drv_bus              :in   std_logic_vector(1023 downto 0);
        
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        -- Measured Transceiver delay 
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        trv_delay            :out  std_logic_vector(G_TRV_CTR_WIDTH - 1 downto 0);
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        ------------------------------------------------------------------------
        -- Prescaler interface
        ------------------------------------------------------------------------
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        -- RX Trigger
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        rx_trigger           :in   std_logic;
        
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        -- TX Trigger
        tx_trigger           :in   std_logic;
        
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        -- Valid synchronisation edge appeared (Recessive to Dominant)
        sync_edge            :out  std_logic;
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        -- Time quanta edge
        tq_edge              :in   std_logic;
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        ------------------------------------------------------------------------
        -- CAN Core Interface
        ------------------------------------------------------------------------
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        -- TX data
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        tx_data_wbs          :in   std_logic;
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        -- RX data
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        rx_data_wbs          :out  std_logic;
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        -- Sample control
        sp_control           :in   std_logic_vector(1 downto 0);
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        -- Reset for Secondary Sampling point Shift register.
        ssp_reset            :in   std_logic;
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        -- Measure transmitter delay
        tran_delay_meas      :in   std_logic; 
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        -- Secondary sampling RX trigger
        sample_sec           :out  std_logic;
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        -- Bit error detected
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        bit_err              :out  std_logic;
        
        -- Reset Bit time measurement counter
        btmc_reset          :in    std_logic;

        -- Start Measurement of data bit time (in TX Trigger)
        dbt_measure_start   :in    std_logic;

        -- First SSP generated (in ESI bit)
        gen_first_ssp       :in    std_logic
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    );
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end entity;

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architecture rtl of bus_sampling is
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    -----------------------------------------------------------------------------
    -- Driving bus aliases
    -----------------------------------------------------------------------------

    -- Enable of the whole driver
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    signal drv_ena              : std_logic;
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    -- Secondary sampling point offset.
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    signal drv_ssp_offset       : std_logic_vector(7 downto 0);
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    -- What value shall be used for ssp_delay (trv_delay, trv_delay+ssp_offset,
    -- ssp_offset)
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    signal drv_ssp_delay_select : std_logic_vector(1 downto 0);
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    -----------------------------------------------------------------------------
    -- Internal registers and signals
    -----------------------------------------------------------------------------
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    -- CAN RX Data (Synchronised)
    signal data_rx_synced       : std_logic;
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    -- Bus sampling and edge detection, Previously sampled value on CAN bus
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    signal prev_Sample          : std_logic;
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    -- Secondary sampling signal (sampling with transciever delay compensation)
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    signal sample_sec_i         : std_logic;
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    -- Delayed TX Data from TX Data shift register at position of secondary
    -- sampling point.
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    signal data_tx_delayed      : std_logic;
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    -- Appropriate edge appeared at recieved data
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    signal edge_rx_valid        : std_logic;
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    -- Edge appeared at transcieved data
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    signal edge_tx_valid        : std_logic;
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    -- Tripple sampling shift register
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    signal trs_reg              : std_logic_vector(2 downto 0);
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    --Note: Bit Error is set up at sample point for whole bit 
    -- time until next sample point!!!!!
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    -- SSP delay. Calculated from trv_delay either directly or by offseting
    -- by ssp_offset.
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    signal ssp_delay            : std_logic_vector(7 downto 0);
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    -- TX Trigger delayed by 1 clock cycle
    signal tx_trigger_q         : std_logic;
    
    -- TX Trigger (used for SSP)
    signal tx_trigger_ssp       : std_logic;
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    ---------------------------------------------------------------------------
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    -- Reset for shift registers. This is used instead of shift register with
    -- preload to lower the resource usage! Resetting and preloading to the
    -- same value can be merged into just resetting by OR of sources
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    ---------------------------------------------------------------------------
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    signal shift_regs_res_d     : std_logic;
    signal shift_regs_res_q     : std_logic;
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    -- Enable for secondary sampling point shift register
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    signal ssp_enable            : std_logic;
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begin
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    ---------------------------------------------------------------------------
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    -- Driving bus aliases
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    ---------------------------------------------------------------------------
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    drv_ena               <= drv_bus(DRV_ENA_INDEX);

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    drv_ssp_offset        <= drv_bus(DRV_SSP_OFFSET_HIGH downto
                                     DRV_SSP_OFFSET_LOW);
    drv_ssp_delay_select  <= drv_bus(DRV_SSP_DELAY_SELECT_HIGH downto
                                     DRV_SSP_DELAY_SELECT_LOW);
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    ----------------------------------------------------------------------------
    -- Synchronisation chain for input signal
    ----------------------------------------------------------------------------
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    can_rx_sig_sync_inst : sig_sync
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    generic map(
        G_RESET_POLARITY     => G_RESET_POLARITY,
        G_RESET_VALUE        => RECESSIVE
    )
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    port map(
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        res_n   => res_n,
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        clk     => clk_sys,
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        async   => can_rx,
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        sync    => data_rx_synced
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    );
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    ---------------------------------------------------------------------------
    -- Component for measurement of transceiver delay and calculation of
    -- secondary sampling point.
    ---------------------------------------------------------------------------
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    trv_delay_measurement_inst : trv_delay_measurement
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    generic map(
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        G_RESET_POLARITY         => G_RESET_POLARITY,
        G_TRV_CTR_WIDTH          => G_TRV_CTR_WIDTH,
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        G_SSP_POS_WIDTH          => G_SSP_POS_WIDTH,
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        G_USE_SSP_SATURATION     => G_USE_SSP_SATURATION,
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        G_SSP_SATURATION_LVL     => G_SSP_DELAY_SAT_VAL
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    )
    port map(
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        clk_sys                => clk_sys,                  -- IN
        res_n                  => res_n,                    -- IN

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        edge_tx_valid          => edge_tx_valid,            -- IN
        edge_rx_valid          => edge_rx_valid,            -- IN
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        tran_delay_meas        => tran_delay_meas,          -- IN
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        ssp_offset             => drv_ssp_offset,           -- IN                    
        ssp_delay_select       => drv_ssp_delay_select,     -- IN
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        trv_delay_shadowed     => trv_delay,                -- OUT
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        ssp_delay_shadowed     => ssp_delay                 -- OUT
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    );
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    ---------------------------------------------------------------------------
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    -- Edge detector on TX, RX Data
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    ---------------------------------------------------------------------------
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    data_edge_detector_inst : data_edge_detector
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    generic map(
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        G_RESET_POLARITY    => G_RESET_POLARITY
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    )
    port map(
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        clk_sys             => clk_sys,         -- IN
        res_n               => res_n,           -- IN
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        tx_data             => tx_data_wbs,     -- IN
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        rx_data             => data_rx_synced,  -- IN
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        prev_rx_sample      => prev_sample,     -- IN
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        tx_edge             => edge_tx_valid,   -- OUT
        rx_edge             => edge_rx_valid    -- OUT
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    );
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    ----------------------------------------------------------------------------
    -- Reset for shift registers for secondary sampling point
    ----------------------------------------------------------------------------
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    shift_regs_res_d <= G_RESET_POLARITY when (ssp_reset = '1') else
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                        (not G_RESET_POLARITY);
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    ----------------------------------------------------------------------------
    -- Pipeline reset for shift registers to avoid glitches!
    ----------------------------------------------------------------------------
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    shift_regs_rst_reg_inst : dff_arst
    generic map(
        G_RESET_POLARITY   => G_RESET_POLARITY,
        
        -- Reset to the same value as is polarity of reset so that other DFFs
        -- which are reset by output of this one will be reset too!
        G_RST_VAL          => G_RESET_POLARITY
    )
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    port map(
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        arst               => res_n,                -- IN
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        clk                => clk_sys,              -- IN
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        input              => shift_regs_res_d,     -- IN
        
        output             => shift_regs_res_q      -- OUT
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    );
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    ----------------------------------------------------------------------------
    -- Create delayed TX Trigger one clock cycle after Stuff pipeline stage.
    ----------------------------------------------------------------------------
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    tx_trigger_reg_inst : dff_arst
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    generic map(
        G_RESET_POLARITY   => G_RESET_POLARITY,
        G_RST_VAL          => '0'
    )
    port map(
        arst               => res_n,                -- IN
        clk                => clk_sys,              -- IN
        input              => tx_trigger,           -- IN
        
        output             => tx_trigger_q          -- OUT
    );

    ----------------------------------------------------------------------------
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    -- Generator of secondary sampling point
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    ----------------------------------------------------------------------------
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    ssp_generator_inst : ssp_generator
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    generic map(
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        G_RESET_POLARITY    => G_RESET_POLARITY,
        G_SSP_CTRS_WIDTH    => G_SSP_CTRS_WIDTH
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    )
    port map(
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        -- Clock and Async reset
        clk_sys             => clk_sys,             -- (IN)
        res_n               => res_n,               -- (IN)

        -- Control signals
        btmc_reset          => btmc_reset,          -- (IN)
        dbt_measure_start   => dbt_measure_start,   -- (IN)
        gen_first_ssp       => gen_first_ssp,       -- (IN)
        ssp_delay           => ssp_delay,           -- (IN)
        ssp_enable          => ssp_enable,          -- (IN)

        -- Trigger signals
        tx_trigger          => tx_trigger,          -- (IN)
        sample_sec          => sample_sec_i         -- (OUT)
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    );

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    -- Secondary sampling point shift register clock enable
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    ssp_enable <= '1' when (sp_control = SECONDARY_SAMPLE) else
                  '0';
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    ----------------------------------------------------------------------------
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    -- Secondary sampling point input: Delayed TX Trigger gated and available
    -- only during secondary sampling! TX trigger for storing data to TX
    -- cache must be delayed since TX data will be one output of Bit Stuffing
    -- only one clock cycle after TX Trigger!
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    ----------------------------------------------------------------------------
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    tx_trigger_ssp <= '1' when (tx_trigger_q = '1' and
                                sp_control = SECONDARY_SAMPLE)
                          else
                      '0';
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    ----------------------------------------------------------------------------
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    -- TX DATA Cache. Stores TX Data when Sample point enters the SSP shift
    -- register and reads data when Sample point steps out of shift register.
    -- This gets the TX data which correspond to the RX Bit in Secondary
    -- sampling point.
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    ----------------------------------------------------------------------------
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    tx_data_cache_inst : tx_data_cache
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    generic map(
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        G_RESET_POLARITY    => G_RESET_POLARITY,
        G_TX_CACHE_DEPTH    => G_TX_CACHE_DEPTH,
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        G_TX_CACHE_RST_VAL  => RECESSIVE
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    )
    port map(
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        clk_sys           => clk_sys,               -- IN
        res_n             => shift_regs_res_q,      -- IN
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        write             => tx_trigger_ssp,        -- IN
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        read              => sample_sec_i,          -- IN
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        data_in           => tx_data_wbs,           -- IN
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        data_out          => data_tx_delayed        -- OUT
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    );
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    ---------------------------------------------------------------------------
    -- Bit error detector
    ---------------------------------------------------------------------------
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    bit_err_detector_inst : bit_err_detector
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    generic map(
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         G_RESET_POLARITY   => G_RESET_POLARITY
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    )
    port map(
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        clk_sys             => clk_sys,             -- IN
        res_n               => res_n,               -- IN
        drv_ena             => drv_ena,             -- IN
        sp_control          => sp_control,          -- IN
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        rx_trigger          => rx_trigger,          -- IN
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        sample_sec          => sample_sec_i,        -- IN
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        data_tx             => tx_data_wbs,         -- IN
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        data_tx_delayed     => data_tx_delayed,     -- IN
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        data_rx_synced      => data_rx_synced,      -- IN
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        bit_err             => bit_err              -- OUT
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    );
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    ----------------------------------------------------------------------------
    -- Sampling of bus value
    ----------------------------------------------------------------------------
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    sample_mux_inst : sample_mux
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    generic map(
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        G_RESET_POLARITY       => G_RESET_POLARITY
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    )
    port map(
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        clk_sys                => clk_sys,          -- IN
        res_n                  => res_n,            -- IN
        drv_ena                => drv_ena,          -- IN
        sp_control             => sp_control,       -- IN
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        rx_trigger             => rx_trigger,       -- IN
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        sample_sec             => sample_sec_i,     -- IN
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        data_rx_synced         => data_rx_synced,   -- IN
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        prev_sample            => prev_sample       -- OUT
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    );
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    -- Output data propagation - Pipe directly - no delay
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    can_tx      <= tx_data_wbs;
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    -- RX Data for bit destuffing - Output of re-synchroniser.
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    rx_data_wbs <= data_rx_synced;
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    -- As synchroniation edge, valid edge on RX Data is selected!
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    -- Gated by Time Quanta edge so that edges aligned with time
    -- quanta are propagated! 
    sync_edge   <= '1' when (edge_rx_valid = '1' and tq_edge = '1') else
                   '0';
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    -- Registers to output propagation
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    sample_sec  <=  sample_sec_i;
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end architecture;